Silicon Storage Technology Inc.

Non-volatile memory systems and methods

Fast voltage regulators for charge pumps

Sense amplifier for low voltage high speed sensing

Charge pump systems and methods

Sense amplifier for low voltage high speed sensing

Fast voltage regulators for charge pumps

Array of non-volatile memory cells including embedded local and global reference cells and system

Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

Charge pump circuit and a novel capacitor for a memory integrated circuit

Integrated flash memory systems and methods for load compensation

Test circuit and method for multilevel cell flash memory

Integrated power detector with temperature compensation for fully-closed loop control

Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing

Non-volatile memory device with plural reference cells, and method of setting the reference cells

Array of non-volatile memory cells including embedded local and global reference cells and system

Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture

Method of testing an integrated circuit die, and an integrated circuit die

Power line compensation for flash memory sense amplifiers

Array and pitch of non-volatile memory cells

Fast start charge pump for voltage regulators

Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same

Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio

Method and apparatus for testing the connectivity of a flash memory chip

Non-volatile memory cell with buried select gate, and method of making same

Non-volatile memory cell with self aligned floating and erase gates, and method of making same

Test circuit and method for multilevel cell flash memory

Method and apparatus for strapping two polysilicon lines in a semiconductor integrated circuit device

Non-volatile memory device having high speed serial interface

Sub volt flash memory system

Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing

Integrated flash memory systems and methods for load compensation

Sense amplifier for low voltage high speed sensing

Flash memory array system including a top gate memory cell

Integrated power detector with temperature compensation for fully-closed loop control

Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array

Method of testing an integrated circuit die, and an integrated circuit die

Storage element for controlling a logic circuit, and a logic device having an array of such storage elements

Memory device having read cache

Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio

Non-volatile memory device having high speed serial interface

Fast voltage regulators for charge pumps

Non-volatile memory systems and methods including page read and/or configuration features

RF power amplifier

Smart memory card wallet

Array of contactless non-volatile memory cells

Systems and methods for providing nonvolatile memory management in wireless phones

Method and system for calibration of a tank circuit in a phase lock loop

Independent bi-directional margin control per level and independently expandable reference cell levels for flash memory sensing

Flash memory array with a top gate line dynamically coupled to a word line

Test circuit and method for multilevel cell flash memory

Landing pad for use as a contact to a conductive spacer

Flash memory array system including a top gate memory cell

Cross coupled high frequency buffer

Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture

Sub volt flash memory system

Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same

Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing

Programmable serial interface for a semiconductor circuit

Systems and methods for transmission and reception of data including frequency and channel code selection

Charge pump systems and methods

High-speed and low-power differential non-volatile content addressable memory cell and array

Sense amplifier for low voltage high speed sensing

Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation

Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby

Integrated flash memory systems and methods for load compensation

Low complexity synchronization for wireless transmission

Method of trimming semiconductor elements with electrical resistance feedback

Fast voltage regulators for charge pumps

Method and apparatus for strapping two polysilicon lines in a semiconductor integrated circuit device

Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby

Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates

Semiconductor memory array of floating gate memory cells with program/erase and select gates

Multiple-transistor structure systems and methods in which portions of a first transistor and a second transistor are formed from the same layer

Multi-operational amplifier system

Chipset for mobile wallet system

Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Assembly of SIM card and RFID antenna

Compensation of I-Q imbalance in digital transceivers

NOR flash memory

Method and apparatus for testing the connectivity of a flash memory chip

Radio frequency power detector

Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing

Method of making phase change memory device employing thermally insulating voids and sloped trench

Hard disk drive cache memory and playback device

RF passive mixer with DC offset tracking and local oscillator DC bias level-shifting network for reducing even-order distortion

Compensation of I-Q imbalance in digital transceivers

High-speed and low-power differential non-volatile content addressable memory cell and array

Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory

Method for handling a defective top gate of a source-side injection flash memory array

Flash memory array system including a top gate memory cell

Multi-operational amplifier system

High throughput AES architecture

Method of programming a non-volatile memory cell

Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation

Word line voltage boosting circuit and a memory array incorporating same

Single transistor sensing and double transistor sensing for flash memory