Andrew H. Simon

Interconnect structure having subtractive etch feature and damascene feature

Forming air gap

FORMING AIR GAP

Insulating a via in a semiconductor substrate

Interconnect structure and method of forming

INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME

Interconnect structure having substractive etch feature and damascene feature

Fabrication of IC structure with metal plug

Integrated circuit having improved electromigration performance and method of forming same

Interconnect structure having subtractive etch feature and damascene feature

Subsurface wires of integrated chip and methods of forming

Insulating a via in a semiconductor substrate

Detecting a void between a via and a wiring line

Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer

Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement

Alternate dual damascene method for forming interconnects

Stacked via structure for metal fuse applications

Structure with air gap crack stop

Subtractive etch interconnects

Constrained nanosecond laser anneal of metal interconnect structures

Back-end electrically programmable fuse

Selective local metal cap layer formation for improved electromigration behavior

DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING

Selective local metal cap layer formation for improved electromigration behavior

Selective local metal cap layer formation for improved electromigration behavior

REDUNDANT VIA STRUCTURE FOR METAL FUSE APPLICATIONS

ELECTRONIC FUSE WITH RESISTIVE HEATER

Graphene and metal interconnects with reduced contact resistance

Metal fuse structure for improved programming capability

Via-fuse with low dielectric constant

SELECTIVE PASSIVATION OF VIAS

Copper interconnect with CVD liner and metallic cap

Interconnect structure with enhanced reliability

Electronic fuse vias in interconnect structures

Modified via bottom for beol via efuse

Graphene-metal E-fuse

High performance refractory metal / copper interconnects to eliminate electromigration

E-fuse with hybrid metallization

Hybrid graphene-metal interconnect structures

Electronic fuse with resistive heater

Doping of copper wiring structures in back end of line processing

Electronic fuse having a damaged region

Selective local metal cap layer formation for improved electromigration behavior

Modified via bottom for BEOL via efuse

Stacked via structure for metal fuse applications

Graphene and metal interconnects

Electronic fuse vias in interconnect structures

Electronic anti-fuse

E-fuse structures and methods of manufacture

PREVENTION OF THRU-SUBSTRATE VIA PISTONING USING HIGHLY DOPED COPPER ALLOY SEED LAYER

Doping of copper wiring structures in back end of line processing

Stacked via structure for metal fuse applications

Method to resolve hollow metal defects in interconnects

Fuse and integrated conductor

Metal fuse structure for improved programming capability

Back-end electrically programmable fuse

Redundant via structure for metal fuse applications

Method of making a copper interconnect having a barrier liner of multiple metal layers

E-fuse structures and methods of manufacture

Stacked via structure for metal fuse applications

Structure and method to make replacement metal gate and contact metal

Interconnect structure with enhanced reliability

Device and methodology for reducing effective dielectric constant in semiconductor devices

Reliability of wide interconnects

Interconnect structure for integrated circuits having improved electromigration characteristics

Structure and method of forming electrically blown metal fuses for integrated circuits

BARRIER SEQUENCE FOR USE IN COPPER INTERCONNECT METALLIZATION

Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME

Reducing effective dielectric constant in semiconductor devices

METHOD FOR FABRICATING A MICROELECTRONIC CONDUCTOR STRUCTURE

Copper contact via structure using hybrid barrier layer

Device and methodology for reducing effective dielectric constant in semiconductor devices

Device and methodology for reducing effective dielectric constant in semiconductor devices

Electroplated copper interconnection structure, process for making and electroplating bath

Back end interconnect with a shaped interface

Bilayered metal hardmasks for use in dual damascene etch schemes

Bilayered metal hardmasks for use in Dual Damascene etch schemes

Copper recess process with application to selective capping and electroless plating

Interconnect structure improvements

Method of forming a metal layer

Device and methodology for reducing effective dielectric constant in semiconductor devices

Copper recess process with application to selective capping and electroless plating

Back end interconnect with a shaped interface

Crystallographic modification of hard mask properties

Method for depositing metal layers using sequential flow deposition

Method of forming a metal layer using an intermittent precursor gas flow process