Inventor profile of:

Eric G. Liniger

City:

Sandy Hook, Connecticut

Country:

United States

Published Applications:

18

Last publication date:

2026-04-30

Top Assignees for applications by Eric G. Liniger

The entities that hold a legal rights for patent applications filed by inventor Liniger Eric G.:

Recent patent applications by Liniger Eric G.

Eric G. Liniger from Sandy Hook, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-30
US20260123395A1
Electricity

AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

#2 | 2024-03-07
US20240079266A1
Electricity

Air gap spacer formation for nano-scale semiconductor devices

#3 | 2019-08-29
US20190267279A1
Electricity

Air gap spacer formation for nano-scale semiconductor devices

#4 | 2018-09-13
US20180261494A1
Electricity

Air gap spacer formation for nano-scale semiconductor devices

#5 | 2018-02-15
US20180047617A1
Electricity

Air gap spacer formation for nano-scale semiconductor devices

#6 | 2018-02-15
US20180047615A1
Electricity

Air gap spacer formation for nano-scale semiconductor devices

#7 | 2017-10-05
US20170284913A1
Physics

Predicting semiconductor package warpage

#8 | 2016-10-06
US20160290905A1
Physics

Predicting semiconductor package warpage

#9 | 2016-05-26
US20160148867A1
Electricity

Nanoscale interconnect structure

#10 | 2015-08-13
US20150228572A1
Electricity

Nanoscale interconnect structure

#11 | 2013-02-28
US20130049207A1
Electricity

Multiple step anneal method and semiconductor formed by multiple step anneal

#12 | 2010-02-04
US20100028695A1
Electricity

Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties

#13 | 2009-08-11
US12357721
-

Crack trapping and arrest in thin film structures

#14 | 2009-02-17
US12060937
-

Method of forming crack trapping and arrest in thin film structures

#15 | 2009-02-05
US20090035480A1
Electricity

Strengthening of a structure by infiltration

#16 | 2008-04-03
US20080079176A1
Electricity

METHOD AND STRUCTURE TO ENHANCE TEMPERATURE/HUMIDITY/BIAS PERFORMANCE OF SEMICONDUCTOR DEVICES BY SURFACE MODIFICATION

#17 | 2007-01-16
US10694500
-

Edge seal for a semiconductor device

#18 | 2006-09-14
US20060202311A1
Electricity

Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties

InventorID:

1257964 ⎘