San Jose, California
United States
38
2024-07-04
38
2024-08-27
These are the the leading inventors for applications assigned to Tessera LLC:
Tessera LLC based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
Gate cut with integrated etch stop layer
#2 | 2024-05-02 ✅ Patent 12,033,892 granted on 2024-07-09Structure and method to improve FAV RIE process margin and electromigration
#3 | 2024-03-21 ✅ Patent 12,106,963 granted on 2024-10-01Self aligned pattern formation post spacer etchback in tight pitch configurations
#4 | 2024-03-07 ✅ Patent 11,978,639 granted on 2024-05-07Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic
#5 | 2023-09-07 ✅ Patent 11,776,957 granted on 2023-10-03Gate cut with integrated etch stop layer
#6 | 2022-11-24 ✅ Patent 11,830,845 granted on 2023-11-28Package-on-package assembly with wire bonds to encapsulation surface
#7 | 2022-11-03 ✅ Patent 11,929,286 granted on 2024-03-12Two dimension material fin sidewall
#8 | 2022-06-09 ✅ Patent 11,837,501 granted on 2023-12-05Selective recessing to form a fully aligned via
#9 | 2022-05-26 ✅ Patent 11,881,433 granted on 2024-01-23Advanced copper interconnects with hybrid microstructure
#10 | 2022-05-19 ✅ Patent 11,798,852 granted on 2023-10-24Hybrid-channel nano-sheet FETs
#11 | 2022-04-14 ✅ Patent 11,804,405 granted on 2023-10-31Method of forming copper interconnect structure with manganese barrier layer
#12 | 2022-01-13 ✅ Patent 11,615,988 granted on 2023-03-28FinFET devices
#13 | 2021-12-23 ✅ Patent 11,682,715 granted on 2023-06-20Forming nanosheet transistor using sacrificial spacer and inner spacers
#14 | 2021-11-04 ✅ Patent 11,699,591 granted on 2023-07-11Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic
#15 | 2021-10-28 ✅ Patent 11,574,864 granted on 2023-02-07Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
#16 | 2021-10-28 ✅ Patent 11,610,780 granted on 2023-03-21Alternating hardmasks for tight-pitch line formation
#17 | 2021-09-30 ✅ Patent 11,652,161 granted on 2023-05-16Nanosheet channel-to-source and drain isolation
#18 | 2021-09-30 ✅ Patent 11,552,077 granted on 2023-01-10Gate cut with integrated etch stop layer
#19 | 2021-09-09 ✅ Patent 11,670,510 granted on 2023-06-06Self aligned pattern formation post spacer etchback in tight pitch configurations
#20 | 2021-09-02 ✅ Patent 11,574,844 granted on 2023-02-07Fabrication of a vertical fin field effect transistor with reduced dimensional variations
#21 | 2021-07-15 ✅ Patent 11,676,854 granted on 2023-06-13Selective ILD deposition for fully aligned via with airgap
#22 | 2021-07-08 ✅ Patent 11,522,045 granted on 2022-12-06Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#23 | 2021-07-08 ✅ Patent 11,710,658 granted on 2023-07-25Structure and method to improve FAV RIE process margin and Electromigration
#24 | 2021-07-01 ✅ Patent 11,380,583 granted on 2022-07-05Forming self-aligned vias and air-gaps in semiconductor fabrication
#25 | 2021-06-17 ✅ Patent 11,664,375 granted on 2023-05-30Minimizing shorting between FinFET epitaxial regions
#26 | 2021-06-17 ✅ Patent 11,488,862 granted on 2022-11-01Semiconductor device with reduced via resistance
#27 | 2021-04-15 ✅ Patent 11,581,190 granted on 2023-02-14Method of fabricating semiconductor fins by differentially oxidizing mandrel sidewalls
#28 | 2021-02-18 ✅ Patent 11,424,211 granted on 2022-08-23Package-on-package assembly with wire bonds to encapsulation surface
#29 | 2021-02-11 ✅ Patent 12,087,685 granted on 2024-09-10Semiconductor interconnect structure with double conductors
#30 | 2021-01-28 ✅ Patent 12,062,703 granted on 2024-08-13Self aligned replacement metal source/drain FINFET
#31 | 2020-12-24 ✅ Patent 11,587,830 granted on 2023-02-21Self-forming barrier for use in air gap formation
#32 | 2020-11-05 ✅ Patent 11,538,720 granted on 2022-12-27Stacked transistors with different channel widths
#33 | 2020-08-13 ✅ Patent 11,404,560 granted on 2022-08-02Punch through stopper in bulk finFET device
#34 | 2020-07-23 ✅ Patent 11,557,589 granted on 2023-01-17Air gap spacer for metal gates
#35 | 2020-07-09 ✅ Patent 11,424,365 granted on 2022-08-23Two dimension material fin sidewall
#36 | 2020-02-20 ✅ Patent 11,380,589 granted on 2022-07-05Selective removal of semiconductor fins
#37 | 2019-10-10 ✅ Patent 11,456,354 granted on 2022-09-27Bulk nanosheet with dielectric isolation
#38 | 2019-08-29 ✅ Patent 11,658,062 granted on 2023-05-23Air gap spacer formation for nano-scale semiconductor devices
Also check out TESSERA LLC's (San Jose, United States) applicant profile with 42 patent applications submitted.
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