San Jose, California
United States
31
2025-04-24
31
2026-05-12
These are the the leading inventors for applications assigned to Adeia Semiconductor Solutions LLC:
Adeia Semiconductor Solutions LLC based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
STRUCTURE AND METHOD TO IMPROVE FAV RIE PROCESS MARGIN AND ELECTROMIGRATION
#2 | 2024-12-12 ✅ Patent 12,369,379 granted on 2025-07-22NANOSHEET TRANSISTOR
#3 | 2024-12-12 ✅ Patent 12,550,709 granted on 2026-02-10SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
#4 | 2024-10-31 ✅ Patent 12,550,359 granted on 2026-02-10FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
#5 | 2024-10-17 ✅ Patent 12,183,634 granted on 2024-12-31Selective recessing to form a fully aligned via
#6 | 2024-08-15 ✅ Patent 12,520,567 granted on 2026-01-06HYBRID-CHANNEL NANO-SHEET FETS
#7 | 2024-08-01 ✅ Patent 12,327,730 granted on 2025-06-10TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RANDOM ACCESS MEMORY (SRAM) AND DENSE LOGIC
#8 | 2024-07-25 ✅ Patent 12,136,573 granted on 2024-11-05Fabrication of a vertical fin field effect transistor with reduced dimensional variations
#9 | 2024-06-20 ✅ Patent 12,494,453 granted on 2025-12-09PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE
#10 | 2024-04-11 ✅ Patent 12,154,971 granted on 2024-11-26Forming nanosheet transistor using sacrificial spacer and inner spacers
#11 | 2024-03-21 ✅ Patent 12,218,003 granted on 2025-02-04Selective ILD deposition for fully aligned via with airgap
#12 | 2024-03-14 ✅ Patent 12,166,110 granted on 2024-12-10Nanosheet channel-to-source and drain isolation
#13 | 2024-03-07 ✅ Patent 12,224,203 granted on 2025-02-11Air gap spacer formation for nano-scale semiconductor devices
#14 | 2024-02-15 ✅ Patent 12,237,328 granted on 2025-02-25Minimizing shorting between FinFET epitaxial regions
#15 | 2024-02-01 ✅ Patent 12,376,369 granted on 2025-07-29FINFET DEVICES
#16 | 2024-01-25 ✅ Patent 12,322,601 granted on 2025-06-03Alternating hardmasks for tight-pitch line formation
#17 | 2023-11-09 ✅ Patent 11,955,424 granted on 2024-04-09Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
#18 | 2023-11-09 ✅ Patent 12,532,682 granted on 2026-01-20FABRICATION OF FINS USING VARIABLE SPACERS
#19 | 2023-11-02 ✅ Patent 12,402,403 granted on 2025-08-26AIR GAP SPACER FOR METAL GATES
#20 | 2023-10-19 ✅ Patent 12,482,704 granted on 2025-11-25SELF-FORMING BARRIER FOR USE IN AIR GAP FORMATION
#21 | 2023-09-21 ✅ Patent 12,237,368 granted on 2025-02-25Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
#22 | 2023-09-21 ✅ Patent 12,230,544 granted on 2025-02-18Stacked transistors with different channel widths
#23 | 2023-09-07 ✅ Patent 11,784,095 granted on 2023-10-10Fabrication of a vertical fin field effect transistor with reduced dimensional variations
#24 | 2023-06-22 ✅ Patent 12,369,367 granted on 2025-07-22Bulk Nanosheet with Dielectric Isolation
#25 | 2022-12-22 ✅ Patent 12,387,983 granted on 2025-08-12FORMING SELF-ALIGNED VIAS AND AIR-GAPS IN SEMICONDUCTOR FABRICATION
#26 | 2022-10-20 ✅ Patent 12,119,393 granted on 2024-10-15Punch through stopper in bulk finFET device
#27 | 2022-08-18 ✅ Patent 12,488,986 granted on 2025-12-02SELECTIVE GAS ETCHING FOR SELF-ALIGNED PATTERN TRANSFER
#28 | 2022-03-03 ✅ Patent 11,894,462 granted on 2024-02-06Forming a sacrificial liner for dual channel devices
#29 | 2021-09-09 ✅ Patent 11,901,438 granted on 2024-02-13Nanosheet transistor
#30 | 2021-09-09 ✅ Patent 12,598,786 granted on 2026-04-07FIELD EFFECT TRANSISTOR STRUCTURES
#31 | 2021-08-26 ✅ Patent 12,622,003 granted on 2026-05-05High Density Three-dimensional Integrated Capacitors
Also check out Adeia Semiconductor Solutions LLC's (San Jose, United States) applicant profile with 48 patent applications submitted.
353127 ⎘