Darrell Rinerson

Two-terminal reversibly switchable memory device

Memory element with a reactive metal layer

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Two-terminal reversibly switchable memory device

Memory element with a reactive metal layer

Two-terminal reversibly switchable memory device

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Two-terminal reversibly switchable memory device

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Low read current architecture for memory

Memory element with a reactive metal layer

Two-terminal reversibly switchable memory device

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Two-terminal reversibly switchable memory device

Low read current architecture for memory

Memory element with a reactive metal layer

Device fabrication

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Two Terminal Re Writeable Non Volatile Ion Transport Memory Device

Low read current architecture for memory

Method for fabricating multi-resistive state memory devices

Memory element with a reactive metal layer

Memory device using ion implant isolated conductive metal oxide

Memory Device Using A Dual Layer Conductive Metal Oxide Structure

Threshold device for a memory array

TRI LAYER METAL OXIDE REWRITABLE NON VOLATILE TWO TERMINAL MEMORY ELEMENT

Local bit lines and methods of selecting the same to access memory elements in cross-point arrays

Multi-resistive state memory device with conductive oxide electrodes

Continuous plane of thin-film materials for a two-terminal cross-point memory

Continuous plane of thin-film materials for a two-terminal cross-point memory

Integrated circuit including four layers of vertically stacked embedded re-writeable non-volatile two-terminal memory

Continuous plane of thin-film materials for a two-terminal cross-point memory

Low read current architecture for memory

Device fabrication

Memory cell formation using ion implant isolated conductive metal oxide

Multi-resistive state memory device with conductive oxide electrodes

Memory access circuits and layout of the same for cross-point memory arrays

Multi-terminal reversibly switchable memory device

Two-Terminal Reversibly Switchable Memory Device

Memory using variable tunnel barrier widths

Four vertically stacked memory layers in a non-volatile re-writeable memory device

Low read current architecture for memory

Threshold device for a memory array

Continuous plane of thin-film materials for a two-terminal cross-point memory

Continuous plane of thin-film materials for a two-terminal cross-point memory

Selection device for re-writable memory

Method for fabricating multi-resistive state memory devices

Conductive memory device with conductive oxide electrodes

Method for two-cycle sensing in a two-terminal memory array having leakage current

Method for sensing a signal in a two-terminal memory array having leakage current

Two-cycle sensing in a two-terminal memory array having leakage current

Sensing a signal in a two-terminal memory array having leakage current

Resistive memory device with a treated interface

Two terminal memory array having reference cells

Two terminal memory array having reference cells

Two terminal memory array having reference cells

Laser annealing of complex metal oxides (CMO) memory materials for non-volatile memory integrated circuits

Providing a reference voltage to a cross point memory array

Conductive memory stack with sidewall

Conductive memory stack with sidewall

Multi-resistive state element with reactive metal

Two terminal memory array having reference cells

Cross point memory array with fast access time

Memory using mixed valence conductive oxides

Conductive memory stack with non-uniform width

Movable terminal in a two terminal memory array

Layout of driver sets in a cross point memory array

Multi-resistive state material that uses dopants

Conductive memory device with conductive oxide electrodes

Low temperature deposition of complex metal oxides (CMO) memory materials for non-volatile memory integrated circuits

Cross point memory array with fast access time

Memory array with high temperature wiring

2-terminal trapped charge memory device with voltage switchable multi-level resistance

Providing a reference voltage to a cross point memory array

Memory using variable tunnel barrier widths

Line drivers that use minimal metal layers

Enhanced functionality in a two-terminal memory array

High-density NVRAM

Two terminal memory array having reference cells

Adaptive programming technique for a re-writable conductive memory device

Providing a reference voltage to a cross point memory array

Multi-layer conductive memory device

Memory element having islands

Re-writable memory with multiple memory layers

Memory array of a non-volatile RAM

Non-volatile memory with a single transistor and resistive memory element

Adaptive programming technique for a re-writable conductive memory device

Line drivers that fits within a specified line pitch

Multi-resistive state element with reactive metal

High-density NVRAM

Conductive memory array having page mode and burst mode read capability

Conductive memory array having page mode and burst mode write capability

Cross point memory array exhibiting a characteristic hysteresis

Re-writable memory with multiple memory layers

Cross point array using distinct voltages

Conductive memory stack with non-uniform width

Re-writable memory with non-linear memory element

Memory array of a non-volatile ram

Non-volatile memory with a single transistor and resistive memory element