PAUL S. MCLAUGHLIN

Metallic synapses for neuromorphic and evolvable hardware

Electromigration test structure for Cu barrier integrity and blech effect evaluations

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

Electromigration test structure for Cu barrier integrity and blech effect evaluations

Method and structure for determining thermal cycle reliability

Electromigration resistant via-to-line interconnect

Electromigration resistant via-to-line interconnect

Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

Non-Destructive Electrical Characterization Macro and Methodology for In-Line Interconnect Spacing Monitoring

Structure for modeling stress-induced degradation of conductive interconnects

Method of forming an embedded barrier layer for protection from chemical mechanical polishing process

Method for prediction of premature dielectric breakdown in a semiconductor

Structure for monitoring stress-induced degradation of conductive interconnects

Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via

Laser fuse structures for high power applications

Structure and method for monitoring stress-induced degradation of conductive interconnects

Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via

Embedded barrier for dielectric encapsulation

METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR

Method of forming a crack stop void in a low-k dielectric layer between adjacent fuses

Test structure for locating electromigration voids in dual damascene interconnects