Inventor profile of:

Amit P. Apte

City:

Austin, Texas

Country:

United States

Published Applications:

30

Last publication date:

2026-04-02

Top Assignees for applications by Amit P. Apte

The entities that hold a legal rights for patent applications filed by inventor Apte Amit P.:

Recent patent applications by Apte Amit P.

Amit P. Apte from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-02
US20260093631A1
Physics

SYSTEMS AND METHODS FOR MIXED DIRECTORY ENTRY ORGANIZATION IN PROBE FILTER

#2 | 2026-03-26
US20260086950A1
Physics

SYSTEMS AND METHODS FOR REGION-BASED PROBE FILTER SHOOTDOWN

#3 | 2026-03-26
US20260086941A1
Physics

SYSTEMS AND METHODS FOR HIGH FIDELITY REGION FROM PROBE FILTER ENTRY

#4 | 2026-02-19
US20260050554A1
Physics

SHADOW TAG MANAGEMENT FOR ACCELERATOR PARTITIONS

#5 | 2025-09-23
US18090251
Physics

Shadow tag management for accelerator partitions

#6 | 2025-07-31
US20250245172A1
Physics

SYSTEMS AND METHODS FOR FACILITATING DUAL OWNERSHIP OF CACHE REGIONS

#7 | 2025-07-24
US20250240156A1
Electricity

SYSTEMS AND METHODS RELATING TO CONFIDENTIAL COMPUTING KEY MIXING HAZARD MANAGEMENT

#8 | 2025-07-03
US20250217297A1
Physics

SYSTEMS AND METHODS FOR INDICATING RECENTLY INVALIDATED CACHE LINES

#9 | 2024-07-04
US20240220415A1
Physics

Tiered memory caching

#10 | 2024-07-04
US20240220405A1
Physics

SYSTEMS AND METHODS FOR HOSTING AN INTERLEAVE ACROSS ASYMMETRICALLY POPULATED MEMORY CHANNELS ACROSS TWO OR MORE DIFFERENT MEMORY TYPES

#11 | 2024-06-20
US20240202144A1
Physics

COHERENT BLOCK READ FULFILLMENT

#12 | 2023-06-22
US20230195662A1
Physics

Coherent block read fulfillment

#13 | 2023-06-22
US20230195632A1
Physics

Probe filter directory management

#14 | 2023-02-09
US20230039289A1
Physics

Probe filter retention based low power state

#15 | 2022-12-29
US20220413586A1
Physics

Demand based probe filter initialization after low power state

#16 | 2022-11-01
US17357104
Physics

Probe filter retention based low power state

#17 | 2022-07-28
US20220237117A1
Physics

Region based split-directory scheme to adapt to large cache sizes

#18 | 2021-12-30
US20210406180A1
Physics

Region based directory scheme to adapt to large cache sizes

#19 | 2021-06-24
US20210191865A1
Physics

Zero value memory compression

#20 | 2021-03-04
US20210064545A1
Physics

Home agent based cache transfer acceleration scheme

#21 | 2020-12-24
US20200401519A1
Physics

Region based split-directory scheme to adapt to large cache sizes

#22 | 2020-03-12
US20200081844A1
Physics

Accelerating accesses to private regions in a region-based cache directory scheme

#23 | 2020-03-05
US20200073801A1
Physics

Region based split-directory scheme to adapt to large cache sizes

#24 | 2019-07-04
US20190205280A1
Physics

Cancel and replay protocol scheme to improve ordered bandwidth

#25 | 2019-06-20
US20190188155A1
Physics

Home agent based cache transfer acceleration scheme

#26 | 2019-06-20
US20190188137A1
Physics

Region based directory scheme to adapt to large cache sizes

#27 | 2019-06-13
US20190179758A1
Physics

Cache to cache data transfer acceleration techniques

#28 | 2019-05-09
US20190138465A1
Physics

Method to reduce write responses to improve bandwidth and efficiency

#29 | 2017-12-28
US20170371787A1
Physics

Contended lock request elision scheme

#30 | 2015-10-01
US20150278016A1
Physics

Method and apparatus for encoding erroneous data in an error correction code protected memory

InventorID:

1307283 ⎘