Inventor profile of:

Andre P. Labonte

City:

Mechanicville, New York

Country:

United States

Published Applications:

25

Last publication date:

2025-04-03

Top Assignees for applications by Andre P. Labonte

The entities that hold a legal rights for patent applications filed by inventor Labonte Andre P.:

Recent patent applications by Labonte Andre P.

Andre P. Labonte from Mechanicville, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-04-03
US20250112054A1
Electricity

CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIALS TO REDUCE THICKNESS LOSS

#2 | 2024-09-05
US20240295688A1
Physics

Method for manufacturing optical device structures

#3 | 2024-08-15
US20240274724A1
Electricity

UNIFORM SIGE CHANNEL IN NANOSHEET ARCHITECTURE

#4 | 2023-01-26
US20230021915A1
Physics

Method for manufacturing optical device structures

#5 | 2022-02-17
US20220050241A1
Physics

Method for manufacturing optical device structures

#6 | 2020-11-19
US20200363719A1
Physics

Methods of forming variable-depth device structures

#7 | 2020-10-22
US20200335401A1
Electricity

Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor

#8 | 2020-05-14
US20200152512A1
Electricity

Interconnect structures of semiconductor devices having a via structure through an upper conductive line

#9 | 2020-05-07
US20200144106A1
Electricity

Interconnect structure having reduced resistance variation and method of forming same

#10 | 2020-02-20
US20200058757A1
Electricity

Contact structures

#11 | 2019-11-28
US20190363178A1
Electricity

Gate tie-down enablement with inner spacer

#12 | 2018-12-27
US20180374932A1
Electricity

Gate tie-down enablement with inner spacer

#13 | 2018-10-04
US20180286956A1
Electricity

Methods of forming a semiconductor device with a gate contact positioned above the active region

#14 | 2018-05-31
US20180151433A1
Electricity

Gate tie-down enablement with inner spacer

#15 | 2018-04-17
US15600874
Electricity

Methods of forming a gate contact for a transistor above an active region and the resulting device

#16 | 2017-12-28
US20170372959A1
Electricity

Gate tie-down enablement with inner spacer

#17 | 2017-09-28
US20170278753A1
Electricity

Gate tie-down enablement with inner spacer

#18 | 2017-06-15
US20170170118A1
Electricity

Local interconnect structure including non-eroded contact via trenches

#19 | 2017-06-15
US20170170070A1
Electricity

Gate tie-down enablement with inner spacer

#20 | 2017-06-08
US20170162438A1
Electricity

Gate tie-down enablement with inner spacer

#21 | 2017-02-16
US20170047254A1
Electricity

Gate tie-down enablement with inner spacer

#22 | 2017-02-16
US20170047252A1
Electricity

Gate tie-down enablement with inner spacer

#23 | 2017-02-14
US14964786
Electricity

Local interconnect structure including non-eroded contact via trenches

#24 | 2016-07-19
US14822654
Electricity

Gate tie-down enablement with inner spacer

#25 | 2015-10-29
US20150311082A1
Electricity

Self-aligned gate contact formation

InventorID:

1341979 ⎘