Mitchell Alsup

Architecture and execution for efficient mixed precision computations in single instruction multiple data/thread (SIMD/T) devices

HYBRID MODE GRAPHICS PROCESSING INTERPOLATOR

Micro-coded transcendental instruction execution

Trace-based instruction execution processing

Control flow in a thread-based environment without branching

Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU)

System and method of implementing microcode operations as subroutines

Virtualizing an IOMMU

Instruction cache prefetch based on trace cache eviction

Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots

Cache memory subsystem including a fixed latency R/W pipeline

Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU)

Virtualizing an IOMMU

Chained hybrid input/output memory management unit

Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation

Method for denying probes during proactive synchronization within a computer system

Synchronization arbiter for proactive synchronization within a multiprocessor computer system

Method for proactive synchronization within a computer system

Method for creating critical section code using a software wrapper for proactive synchronization within a computer system

Augmented instruction set for proactive synchronization within a computer system

Method for maintaining atomicity of instruction sequence to access a number of cache lines during proactive synchronization within a computer system

Avoiding silent data corruption and data leakage in a virtual environment with multiple guests

Controlling an I/O MMU

Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)

Cache memory system including a cache memory employing a tag including associated touch bits

Microprocessor including bank-pipelined cache with asynchronous data blocks

Microprocessor including cache memory supporting multiple accesses per cycle

Mapper circuit with backup capability

Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming

System and method of identifying liveness groups within traces stored in a trace cache

Stride-based prefetch mechanism using a prediction confidence value

System and method for validating a memory file that links speculative results of load operations to register values

Scheduler for use in a microprocessor that supports data-speculative execution

Transitioning from instruction cache to trace cache on label boundaries

System and method for handling exceptional instructions in a trace cache based processor