Inventor profile of:

Anthony ASARO

City:

Markham

Country:

Canada

Published Applications:

40

Last publication date:

2026-04-07

Top Assignees for applications by Anthony ASARO

The entities that hold a legal rights for patent applications filed by inventor ASARO Anthony:

Recent patent applications by ASARO Anthony

Anthony ASARO from Markham, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-07
US18170433
Physics

Distributed direct memory operations having DMA engine with frontend and selected backend according to affinity identified based on selected physical address space

#2 | 2026-03-26
US20260086956A1
Physics

CONFIDENTIAL COMPUTING OWNERSHIP CHECK

#3 | 2026-03-12
US20260072599A1
Physics

DYNAMIC REPARTITION OF MEMORY PHYSICAL ADDRESS MAPPING

#4 | 2025-10-02
US20250307475A1
Physics

DEVICES AND SYSTEMS FOR ENFORCING CONFIDENTIAL COMPUTING

#5 | 2025-05-15
US20250156336A1
Physics

INTERMINGLING MEMORY RESOURCES USING MULTIPLE ADDRESSING MODES

#6 | 2025-04-03
US20250110893A1
Physics

CACHE VIRTUALIZATION

#7 | 2025-01-02
US20250004653A1
Physics

DYNAMIC MEMORY RECONFIGURATION

#8 | 2024-12-19
US20240419358A1
Physics

HARDWARE MANAGEMENT OF DIRECT MEMORY ACCESS COMMANDS

#9 | 2024-10-03
US20240330199A1
Physics

SECURE MEMORY ACCESS IN A VIRTUALIZED COMPUTING ENVIRONMENT

#10 | 2024-10-03
US20240329720A1
Physics

STORING CONTIGUOUS DISPLAY CONTENT IN EACH DRAM FOR IDLE STATIC SCREEN POWER SAVING

#11 | 2024-06-20
US20240202047A1
Physics

SYSTEMS AND METHODS FOR CHIPLET SYNCHRONIZATION

#12 | 2024-06-20
US20240201876A1
Physics

Method and apparatus for managing memory

#13 | 2024-01-04
US20240004562A1
Physics

Dynamic memory reconfiguration

#14 | 2023-12-14
US20230401159A1
Physics

MEMORY POOLS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM

#15 | 2023-11-30
US20230384947A1
Physics

DYNAMIC REPARTITION OF MEMORY PHYSICAL ADDRESS MAPPING

#16 | 2023-05-04
US20230132931A1
Physics

DMA engines configured to perform first portion data transfer commands with a first DMA engine and second portion data transfer commands with second DMA engine

#17 | 2023-03-30
US20230097344A1
Physics

Dynamic repartition of memory physical address mapping

#18 | 2023-02-23
US20230055695A1
Physics

VMID as a GPU task container for virtualization

#19 | 2022-12-29
US20220414016A1
Physics

CONCURRENT PROCESSING OF MEMORY MAPPING INVALIDATION REQUESTS

#20 | 2022-08-25
US20220269620A1
Physics

Access log and address translation log for a processor

#21 | 2021-12-30
US20210406196A1
Physics

Memory pools in a memory model for a unified computing system

#22 | 2021-02-18
US20210049030A1
Physics

GRAPHICS PROCESSING UNIT PROFILING TOOL VIRTUALIZATION

#23 | 2021-01-14
US20210011760A1
Physics

VMID as a GPU task container for virtualization

#24 | 2020-06-25
US20200201758A1
Physics

Virtualized input/output device local memory management

#25 | 2020-06-18
US20200192825A1
Physics

SECURITY FOR VIRTUALIZED DEVICE

#26 | 2020-05-28
US20200167291A1
Physics

Dynamic remapping of virtual address ranges using remap vector

#27 | 2020-04-30
US20200133878A1
Physics

Secure memory access in a virtualized computing environment

#28 | 2020-01-14
US16228360
Physics

Storing microcode for a virtual function in a trusted memory region

#29 | 2019-10-03
US20190303302A1
Physics

Memory pools in a memory model for a unified computing system

#30 | 2019-01-17
US20190018699A1
Physics

Hang detection for virtualized accelerated processing device

#31 | 2019-01-03
US20190004840A1
Physics

Register partition and protection for virtualized processing device

#32 | 2019-01-03
US20190004839A1
Physics

Early virtualization context switch for virtualized accelerated processing device

#33 | 2018-12-06
US20180349165A1
Physics

Direct doorbell ring in virtualized processing device

#34 | 2018-10-25
US20180307619A1
Physics

Input/output memory map unit and northbridge

#35 | 2018-06-28
US20180181488A1
Physics

High-speed selective cache invalidates and write-backs on GPUS

#36 | 2018-01-18
US20180018221A1
Physics

DDR memory error recovery

#37 | 2018-01-11
US20180011798A1
Physics

Memory heaps in a memory model for a unified computing system

#38 | 2016-12-22
US20160371197A1
Physics

MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM

#39 | 2016-12-15
US20160364334A1
Physics

Managing coherent memory between an accelerated processing device and a central processing unit

#40 | 2015-12-17
US20150363310A1
Physics

Memory heaps in a memory model for a unified computing system

InventorID:

1394720 ⎘