Inventor profile of:

Yasuko Eckert

City:

Redmond, Washington

Country:

United States

Published Applications:

19

Last publication date:

2026-01-01

Top Assignees for applications by Yasuko Eckert

The entities that hold a legal rights for patent applications filed by inventor Eckert Yasuko:

Recent patent applications by Eckert Yasuko

Yasuko Eckert from Redmond, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-01
US20260003576A1
Physics

Near-Memory Random and Pattern-Based Number Generation

#2 | 2024-10-03
US20240329984A1
Physics

Lookup Table (LUT) Vector Instruction

#3 | 2024-07-04
US20240220247A1
Physics

Permute Instructions for Register-Based Lookups

#4 | 2024-05-16
US20240160364A1
Physics

Allocation of resources when processing at memory level through memory request scheduling

#5 | 2024-03-28
US20240103745A1
Physics

Scheduling Processing-in-Memory Requests and Memory Requests

#6 | 2024-01-04
US20240004584A1
Physics

DRAM row management for processing in memory

#7 | 2023-06-29
US20230205693A1
Physics

Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host

#8 | 2023-05-18
US20230153218A1
Physics

Chiplet-level performance information for configuring chiplets in a processor

#9 | 2023-03-30
US20230094508A1
Physics

Running instances of a quantum program concurrently on a quantum processor

#10 | 2021-06-17
US20210182216A1
Physics

Cache management based on access type priority

#11 | 2021-06-17
US20210182213A1
Physics

CACHE LINE RE-REFERENCE INTERVAL PREDICTION USING PHYSICAL PAGE ADDRESS

#12 | 2021-06-10
US20210173796A1
Physics

Memory request priority assignment techniques for parallel processors

#13 | 2019-04-25
US20190123648A1
Electricity

Setting operating points for circuits in an integrated circuit chip

#14 | 2019-02-28
US20190065243A1
Physics

DYNAMIC MEMORY POWER CAPPING WITH CRITICALITY AWARENESS

#15 | 2018-10-09
US15793951
Electricity

Setting operating points for circuits in an integrated circuit chip

#16 | 2018-09-27
US20180276150A1
Physics

Dynamic memory remapping to reduce row-buffer conflicts

#17 | 2018-04-26
US20180115496A1
Electricity

MECHANISMS TO IMPROVE DATA LOCALITY FOR DISTRIBUTED GPUS

#18 | 2017-12-28
US20170371719A1
Physics

Temperature-aware task scheduling and proactive power management

#19 | 2016-03-24
US20160086654A1
Physics

Thermal aware data placement and compute dispatch in a memory system

InventorID:

1484342 ⎘