Inventor profile of:

Arvind Kamath

City:

Mountain View, California

Country:

United States

Published Applications:

36

Last publication date:

2017-05-02

Top Assignees for applications by Arvind Kamath

The entities that hold a legal rights for patent applications filed by inventor Kamath Arvind:

Recent patent applications by Kamath Arvind

Arvind Kamath from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2017-05-02
US13889243
Electricity

Method for modifying and controlling the threshold voltage of thin film transistors

#2 | 2016-02-04
US20160035762A1
Electricity

Methods for Manufacturing RFID Tags and Structures Formed Therefrom

#3 | 2015-05-28
US20150146345A1
Electricity

Methods for forming electrically precise capacitors on insulative substrates, and structures formed therefrom

#4 | 2015-03-10
US13868916
Electricity

Methods for forming electrically precise capacitors, and structures formed therefrom

#5 | 2014-10-09
US20140299883A1
Electricity

PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR

#6 | 2014-04-03
US20140094004A1
Electricity

Printed dopant layers

#7 | 2014-04-03
US20140091909A1
Electricity

Surveillance devices with multiple capacitors

#8 | 2013-12-26
US20130344301A1
Chemistry; metallurgy

Print processing for patterned conductor, semiconductor and dielectric materials

#9 | 2013-07-25
US20130189823A1
Electricity

Profile engineered thin film devices and structures

#10 | 2013-06-11
US12357065
-

Method for modifying and controlling the threshold voltage of thin film transistors

#11 | 2013-05-21
US12249841
-

High precision capacitors

#12 | 2013-03-21
US20130069785A1
Physics

High reliability surveillance and/or identification tag/devices and methods of making and using the same

#13 | 2012-12-06
US20120307569A1
Electricity

Printed non-volatile memory

#14 | 2012-07-19
US20120181636A1
Electricity

Method of forming metal silicide contact and metal interconnect

#15 | 2011-09-20
US12574426
-

Method characterizing materials for a trench isolation structure having low trench parasitic capacitance

#16 | 2011-01-27
US20110017997A1
Electricity

Diffusion barrier coated substrates and methods of making the same

#17 | 2010-09-30
US20100244133A1
Electricity

Printed dopant layers

#18 | 2010-07-01
US20100163962A1
Electricity

Printed non-volatile memory

#19 | 2010-06-17
US20100148859A1
Electricity

Methods for manufacturing RFID tags and structures formed therefrom

#20 | 2010-05-20
US20100123582A1
Physics

Method for making surveillance devices with multiple capacitors

#21 | 2009-11-17
US11262173
-

Shallow trench isolation structure with low trench parasitic capacitance

#22 | 2009-05-28
US20090137071A1
Physics

High reliability surveillance and/or identification tag/devices and methods of making and using the same

#23 | 2009-04-30
US20090109035A1
Physics

High reliability surveillance and/or identification tag/devices and methods of making and using the same

#24 | 2009-04-02
US20090085095A1
Electricity

Profile engineered, electrically active thin film devices

#25 | 2009-03-12
US20090065776A1
Chemistry; metallurgy

Print processing for patterned conductor, semiconductor and dielectric materials

#26 | 2009-01-22
US20090020829A1
Electricity

Methods of making metal silicide contacts, interconnects, and/or seed layers

#27 | 2008-08-19
US10413051
-

High k gate insulator removal

#28 | 2008-02-28
US20080048240A1
Electricity

Printed non-volatile memory

#29 | 2008-02-21
US20080044964A1
Electricity

Printed dopant layers

#30 | 2008-02-21
US20080042212A1
Electricity

Printed dopant layers

#31 | 2007-12-13
US20070287237A1
Electricity

Printed, self-aligned, top gate thin film transistor

#32 | 2007-01-11
US20070007342A1
Electricity

Methods for manufacturing RFID tags and structures formed therefrom

#33 | 2006-04-11
US10697446
-

Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate

#34 | 2006-02-21
US9991202
-

Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance

#35 | 2005-09-27
US10457942
-

Method of shallow trench isolation formation and planarization

#36 | 2005-01-13
US20050006347A1
Electricity

Hard mask removal

InventorID:

149005 ⎘