LSI LOGIC CORPORATION

Integrated circuit cell architecture configurable for memory or logic elements

Method characterizing materials for a trench isolation structure having low trench parasitic capacitance

Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures

Determination of film thickness during chemical mechanical polishing

Enhanced power distribution in an integrated circuit

Semiconductor package and method using isolated Vplane to accommodate high speed circuitry ground isolation

Synthesized logic replacement

Adjustable EMI baffling method for data storage systems

Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board

Latch-based random access memory

Identification circuit with repeatable output code

Flipchip bump patterns for efficient I-mesh power distribution schemes

Arrangement and method for fabricating a semiconductor wafer

On-chip circuit for transition delay fault test pattern generation with launch off shift

Semiconductor package having increased resistance to electrostatic discharge

Shoulder screw and handle drive mounting system

Integrated circuit package with sputtered heat sink for improved thermal performance

Cryptographic random number generator using finite field operations

High throughput pipelined data path

Package configuration and manufacturing method enabling the addition of decoupling capacitors to standard package designs

Efficient hardware implementation of tweakable block cipher

Method and apparatus for adjusting on-chip delay with power supply control

Power saving flip-flop

Enhancing performance of SATA disk drives in SAS domains

Generic methodology to support chip level integration of IP core instance constraints in integrated circuits

Dual porting serial advanced technology attachment disk drives for fault tolerant applications

Pipelined LDPC arithmetic unit

Low complexity LDPC encoding algorithm

Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)

Low area architecture in BCH decoder

System and method for compensating for PVT variation effects on the delay line of a clock signal

Polymorphic management of embedded devices using web interfaces

Method and apparatus for booting independent operating systems in a multi-processor core integrated circuit

Methods and systems for load balancing of virtual machines in clustered processors using storage related load information

Methods and structure for improved testing of embedded systems

Parallel LDPC decoder

Method for redirecting void diffusion away from vias in an integrated circuit design

Wire bond integrated circuit package for high speed I/O

Digital power-on reset

Flow control enhancement

Forward packet data channel with parallel sub-packets

Circuit, systems and methods for monitoring storage controller status

Substrate laser marking

Built in self test transport controller architecture

Efficient 8×8 CABAC residual block transcode system

Enhanced personal video recorder

Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes

Method and apparatus for using and combining sub-frame processing and adaptive jitter-buffers for improved voice quality in voice-over-packet networks

Method of forming a low k polymer E-beam printable mechanical support

Secure, stable on chip silicon identification

Low mutual inductance matched inductors

System and method for providing swap path voltage and temperature compensation

Random seed stability with fuses

Efficient high density voice processor

Stabilization for random chip identifier circuit

Voltage contrast monitor for integrated circuit defects

Serial data transmitter with bit doubling

Single engine turbo decoder with single frame size buffer for interleaving/deinterleaving

Method and apparatus for fixing best case hold time violations in an integrated circuit design

Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction

Data shredding RAID mode

Integrated circuit package and system interface

Electroplating tool for semiconductor manufacture having electric field control

Method and/or apparatus for paging to a dynamic memory array

Grooming switch hardware scheduler

Method for improving rate-distortion performance of a video compression system through parallel coefficient cancellation in the transform

Method of vaporizing and ionizing metals for use in semiconductor processing

Method, system and programming language for device diagnostics and validation

Intelligent recording control system

Virtual path for interconnect fabric using bandwidth process

Density driven layout for RRAM configuration module

Arithmetic decode without renormalization costs

Interface circuit for providing a computer logic circuit with first and second voltages and an associated method

Method for using CRC as metadata to protect against drive anomaly errors in a storage array

Reactor system

Advanced high density data write strategy

Sequential tester for longest prefix search engines

Differential current-mode driver with high common-mode range and controlled edge rates

Ramptime propagation on designs with cycles

Digital Gaussian noise simulator

Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures

Verification of an extracted timing model file

Scaled coercion of disk drive capacity

Converter circuit for converting 1-redundant representation of an integer

Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)

Storing RAID configuration data within a BIOS image

Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics

Yield-limiting design-rules-compliant pattern library generation and layout inspection

Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction

System for avoiding false path pessimism in estimating net delay for an integrated circuit design

Memory timing model with back-annotating

Method and apparatus for dynamically selecting one of multiple firmware images for booting an I/O controller