Austin, Texas
United States
51
2024-12-19
The entities that hold a legal rights for patent applications filed by inventor Ignatowski Michael:
Michael Ignatowski from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Flexible, scalable graph-processing accelerator
#2 | 2024-10-03MEMORY SPRINTING
#3 | 2024-10-03Memory sprinting
#4 | 2024-08-15Multi-Stack Compute Chip and Memory Architecture
#5 | 2024-03-143D LAYOUT AND ORGANIZATION FOR ENHANCEMENT OF MODERN MEMORY SYSTEMS
#6 | 2024-03-14HYBRID MEMORY ARCHITECTURE FOR ADVANCED 3D SYSTEMS
#7 | 2024-03-14Error Correction for Stacked Memory
#8 | 2024-03-14Dynamic Memory Operations
#9 | 2024-03-14FERROELECTRIC RANDOM-ACCESS MEMORY WITH ENHANCED LIFETIME, DENSITY, AND PERFORMANCE
#10 | 2024-03-14REGISTER, FLOP, AND LATCH DESIGNS INLCUDING FERROELECTRIC AND LINEAR DIELECTRICS
#11 | 2023-11-02METHOD AND APPARATUS OF INTEGRATING MEMORY STACKS
#12 | 2023-08-03Device and method for accelerating matrix multiply operations
#13 | 2022-11-17Flexible, scalable graph-processing accelerator
#14 | 2022-11-17DATA STRUCTURE ENGINE
#15 | 2022-06-30Providing host-based error detection capabilities in a remote execution device
#16 | 2022-05-19Method for a reliability, availability, and serviceability-conscious huge page support
#17 | 2022-03-31Error detection and correction in memory modules using programmable ECC engines
#18 | 2021-07-08Device and method for accelerating matrix multiply operations
#19 | 2021-06-03Method for a reliability, availability, and serviceability-conscious huge page support
#20 | 2020-04-30Device and method for accelerating matrix multiply operations as a sum of outer products
#21 | 2020-04-30Device and method for accelerating matrix multiply operations
#22 | 2020-04-30Tolerating memory stack failures in multi-stack systems
#23 | 2020-02-20Data processing system with decoupled data operations
#24 | 2019-07-18Near-memory hardened compute blocks for configurable computing substrates
#25 | 2018-11-29Method and apparatus of integrating memory stacks
#26 | 2018-03-01Nondeterministic memory access requests to non-volatile memory
#27 | 2017-10-26Memory object tagged memory monitoring method and system
#28 | 2017-05-25COMPUTATION ALONG A DATAPATH BETWEEN MEMORY BLOCKS
#29 | 2017-03-23Multi-protocol header generation system
#30 | 2016-08-25MEMORY MODULE WITH VOLATILE AND NON-VOLATILE STORAGE ARRAYS
#31 | 2016-08-11Memory page access detection
#32 | 2016-06-23Techniques for changing management modes of multilevel memory hierarchy
#33 | 2016-06-02MEMORY PERSISTENCE MANAGEMENT CONTROL
#34 | 2015-11-12System and method for memory allocation in a multiclass memory system
#35 | 2015-10-22Methods and systems for mitigating memory drift
#36 | 2015-09-17ADDRESS-PARTITIONED MULTI-CLASS PHYSICAL MEMORY SYSTEM
#37 | 2015-06-04Die-stacked memory device with reconfigurable logic
#38 | 2015-04-02Latency-aware memory control
#39 | 2014-06-26Computation memory operations in a logic layer of a stacked memory
#40 | 2014-06-26Die-stacked memory device providing data translation
#41 | 2014-06-26Write endurance management techniques in the logic layer of a stacked memory
#42 | 2014-06-26Quality of service support using stacked memory device with logic die
#43 | 2014-06-26Compound Memory Operations in a Logic Layer of a Stacked Memory
#44 | 2014-06-26Cache coherency using die-stacked memory device with logic die
#45 | 2014-06-26PREFETCHING FUNCTIONALITY ON A LOGIC DIE STACKED WITH MEMORY
#46 | 2014-06-26Die-stacked memory device with reconfigurable logic
#47 | 2014-02-06Stacked memory device with metadata management
#48 | 2014-02-06STACKED MEMORY DEVICE WITH HELPER PROCESSOR
#49 | 2013-06-20MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS
#50 | 2013-03-21Method and apparatus for controlling state information retention in an apparatus
#51 | 2012-12-13SYSTEMS AND METHODS FOR SHARING MEMORY BETWEEN A PLURALITY OF PROCESSORS
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