Folsom, California
United States
44
2026-06-25
The entities that hold a legal rights for patent applications filed by inventor GARG ASHUTOSH:
ASHUTOSH GARG from Folsom, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MIXED-PRECISION MATRIX MULTIPLICATION
#2 | 2026-04-02UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
#3 | 2025-06-26SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
#4 | 2025-05-22ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
#5 | 2025-04-24MULTI-FORMAT OPERAND CIRCUIT
#6 | 2025-04-24FLOATING POINT BIAS SWITCHING
#7 | 2025-04-24STOCHASTIC ROUNDING CIRCUIT
#8 | 2025-04-24FLOATING-POINT CONVERSION CIRCUIT
#9 | 2025-03-27ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
#10 | 2024-12-26SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS
#11 | 2024-10-31GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUCT ACCUMULATE INSTRUCTION FOR HYBRID FLOATING POINT FORMAT
#12 | 2024-09-26UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
#13 | 2024-05-16Architecture for block sparse operations on a systolic array
#14 | 2024-02-15SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES
#15 | 2023-11-02Sparse optimizations for a matrix accelerator architecture
#16 | 2023-09-21INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE
#17 | 2023-09-07Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
#18 | 2023-06-22Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#19 | 2022-11-17Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#20 | 2022-10-13Instructions and logic for vector multiply add with zero skipping
#21 | 2022-08-18Compiler assisted register file write reduction
#22 | 2022-06-30SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES
#23 | 2022-06-02Sparse matrix multiplication acceleration mechanism
#24 | 2022-05-19Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
#25 | 2022-04-28Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#26 | 2021-12-02Sparse optimizations for a matrix accelerator architecture
#27 | 2021-11-11Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
#28 | 2021-10-07Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
#29 | 2021-09-30Instruction and logic for systolic dot product with accumulate
#30 | 2021-06-24Compiler assisted register file write reduction
#31 | 2021-06-24Instructions and logic for vector multiply add with zero skipping
#32 | 2021-05-13Dot product multiplier mechanism
#33 | 2021-04-08Dot product operations on sparse matrix elements
#34 | 2021-03-25Sharing register file usage between fused processing resources
#35 | 2021-03-18Utilizing structured sparsity in systolic arrays
#36 | 2021-03-11Sparse matrix multiplication acceleration mechanism
#37 | 2021-02-04Sparse optimizations for a matrix accelerator architecture
#38 | 2020-01-02Register bank conflict reduction for multi-threaded processor
#39 | 2019-11-28Software scoreboard information and synchronization
#40 | 2019-10-24Instruction and logic for systolic dot product with accumulate
#41 | 2019-08-29Fusion of SIMD Processing Units
#42 | 2019-07-23Software scoreboard information and synchronization
#43 | 2016-12-29Handling instructions that require adding results of a plurality of multiplications
#44 | 2016-06-30Reduced power implementation of computer instructions
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