Yasuko Eckert

SYSTEMS AND METHODS FOR EXECUTING AN INSTRUCTION BY AN ARITHMETIC LOGIC UNIT PIPELINE

LOAD INSTRUCTION DIVISION

DEVICE, SYSTEM, AND METHOD FOR CONSOLIDATING ELIGIBLE VECTOR INSTRUCTIONS

EVENT-TRIGGERED DYNAMIC POWER MANAGEMENT

SCHEDULING USING COLLAPSED OPERATIONS

DEVICES, SYSTEMS, AND METHODS FOR DETECTING AND MITIGATING SILENT DATA CORRUPTIONS VIA ADAPTIVE VOLTAGE-FREQUENCY SCALING

Devices, systems, and methods for detecting and mitigating silent data corruptions via adaptive voltage-frequency scaling

SYSTEMS AND METHODS FOR INTERPOLATING REGISTER-BASED LOOKUP TABLES

METHOD FOR EMBEDDING ROWS PREFETCHING IN RECOMMENDATION MODELS

Register based SIMD lookup table operations

Distribution of data and memory timing parameters across memory modules based on memory access patterns

Quantum circuit mapping for multi-programmed quantum computers

ARTIFICIAL INTELLIGENCE VIA HARDWARE-ASSISTED TOURNAMENT

Distribution of data and memory timing parameters across memory modules based on memory access patterns

WORKLOAD BASED TUNING OF MEMORY TIMING PARAMETERS

METHODS FOR CONFIGURING SPAN OF CONTROL UNDER VARYING TEMPERATURE

Dynamically configurable overprovisioned microprocessor

Memory access response merging in a memory hierarchy

Interconnect architecture for three-dimensional processing systems

Look-ahead teleportation for reliable computation in multi-SIMD quantum processor

Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory

Method and system for opportunistic load balancing in neural networks using metadata

Variation-aware qubit movement scheme for noise intermediate scale quantum era computers

Adaptive cache management based on programming model information

Cache management based on reuse distance

Adaptive cache reconfiguration via clustering

Distributed coherence directory subsystem with exclusive data regions

Mechanism for dynamic latency-bandwidth trade-off for efficient broadcasts/multicasts

Mechanism for distributed-system-aware difference encoding/decoding in graph analytics

Coherency directory entry allocation based on eviction costs

Method and system for opportunistic load balancing in neural networks using metadata

Distributed coherence directory subsystem with exclusive data regions

Prioritizing local and remote memory access in a non-uniform memory access architecture

Selective data retrieval based on access latency

Lightweight address translation for page migration and duplication

Reducing cache footprint in cache coherence directory

Mechanism for reducing page migration overhead in memory systems

Preemptive cache management policies for processing units

Proactive cache coherence

CACHE ENTRY REPLACEMENT BASED ON PENALTY OF MEMORY ACCESS

Method and apparatus for performing memory prefetching

Hierarchical register file at a graphics processing unit

Interconnect architecture for three-dimensional processing systems

DISTRIBUTED MEMORY CONTROLLER

CONFIGURING FAST MEMORY AS CACHE FOR SLOW MEMORY

Thermally-aware throttling in a three-dimensional processor stack

CONTROL OF THERMAL ENERGY TRANSFER FOR PHASE CHANGE MATERIAL IN DATA CENTER

CHANGING POWER LIMITS BASED ON DEVICE STATE

Pruning of low power state information for a processor

Query operations for stacked-die memory device