BRIAN K. KIRKPATRICK

INTEGRATED WET CLEAN FOR BEVEL TREATMENTS

INTEGRATED WET CLEAN FOR EPITAXIAL GROWTH

METHODS OF FABRICATING HIGH-K GATE STRUCTURES

REDUCED SEMICONDUCTOR WAFER BOW AND WARPAGE

PROCESSING METHODS AND CLUSTER TOOLS FOR FORMING SEMICONDUCTOR DEVICES

Cleaning method with in-line SPM processing

Surface cleaning with directed high pressure chemistry

Reduced semiconductor wafer bow and warpage

INTEGRATEAD WET CLEAN FOR BEVEL TREATMENTS

INTEGRATED WET CLEAN FOR GATE STACK DEVELOPMENT

INTEGRATED WET CLEAN FOR EPITAXIAL GROWTH

Cleaning system with in-line SPM processing

Split gate memory cell fabrication and system

Method for stripping one or more layers from a semiconductor wafer

Dopant anneal with stabilization step for IC with matched devices

Integrated circuit having chemically modified spacer surface

Method of fabricating semiconductors

Method of fabricating semiconductors

Inner L-spacer for replacement gate flow

Integrated circuit having chemically modified spacer surface

GATE SLOT OVERETCH CONTROL

Integrated circuit having chemically modified spacer surface

Inner L-spacer for replacement gate flow

High-k / metal gate CMOS transistors with TiN gates

Inner L-spacer for replacement gate flow

High-k / metal gate CMOS transistors with TiN gates

Inner L-spacer for replacement gate flow

Hard mask for source/drain epitaxy control

FABRICATING A SEMICONDUCTOR DIE HAVING COEFFICIENT OF THERMAL EXPANSION GRADED LAYER

INTEGRATED CIRCUIT HAVING CHEMICALLY MODIFIED SPACER SURFACE

MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls

Die having coefficient of thermal expansion graded layer

Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls

Gate dielectric first replacement gate processes and integrated circuits therefrom

Wafer planarity control between pattern levels

Curvature reduction for semiconductor wafers

Nitride removal while protecting semiconductor surfaces for forming shallow junctions

Post high-k dielectric/metal gate clean

Cross-contamination control for semiconductor process flows having metal comprising gate electrodes

Cross-contamination control for processing of circuits comprising MOS devices that include metal comprising high-K dielectrics

Post metal gate VT adjust etch clean

Gate dielectric first replacement gate processes and integrated circuits therefrom

Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom

Method to Form CMOS Circuits Using Optimized Sidewalls

METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH

SHALLOW TRENCH DIVOT CONTROL POST

Recessed STI for wide transistors

Chemical Mechanical Polishing Method and Apparatus

Systems and methods for removing wafer edge residue and debris using a residue remover mechanism

Systems and methods for removing wafer edge residue and debris using a wafer clean solution

Protection of silicon from phosphoric acid using thick chemical oxide

Dual-gate integrated circuit semiconductor device

Chemical mechanical polishing method and apparatus

Post high voltage gate dielectric pattern plasma surface treatment

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits

Method for improving a physical property defect value of a gate dielectric

Chemical mechanical polishing method and apparatus

Post plasma clean process for a hardmask

Nickel silicide - silicon nitride adhesion through surface passivation

Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits

Method for improving a physical property defect value of a gate dielectric

Pre-pattern surface modification of low-k dielectrics