Inventor profile of:

Rishabh Jain

City:

Austin, Texas

Country:

United States

Published Applications:

19

Last publication date:

2025-06-12

Top Assignees for applications by Rishabh Jain

The entities that hold a legal rights for patent applications filed by inventor Jain Rishabh:

Recent patent applications by Jain Rishabh

Rishabh Jain from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-06-12
US20250190221A1
Physics

SYSTEMS AND METHODS FOR PARALLELIZATION OF EMBEDDING OPERATIONS

#2 | 2025-05-08
US20250147681A1
Physics

On-Chip Atomic Transaction Engine

#3 | 2024-08-01
US20240256406A1
Physics

Traffic isolation at a chip-to-chip gateway of a data processing system

#4 | 2024-04-04
US20240111441A1
Physics

On-chip atomic transaction engine

#5 | 2022-11-03
US20220350771A1
Physics

CCIX port management for PCI express traffic

#6 | 2022-09-01
US20220276794A1
Physics

On-chip atomic transaction engine

#7 | 2021-07-27
US17036225
Physics

Message protocol for a data processing system

#8 | 2020-11-19
US20200363967A1
Physics

On-chip atomic transaction engine

#9 | 2019-10-24
US20190324939A1
Physics

Processor core to coprocessor interface with FIFO semantics

#10 | 2018-11-15
US20180329975A1
Physics

Tuple encoding aware direct memory access engine for scratchpad enabled multi-core processors

#11 | 2018-05-31
US20180150542A1
Physics

Database tuple-encoding-aware data partitioning in a direct memory access engine

#12 | 2018-05-31
US20180150421A1
Physics

Multicast copy ring for database direct memory access filtering engine

#13 | 2018-05-31
US20180150407A1
Physics

Row identification number generation in database direct memory access engine

#14 | 2018-05-31
US20180150259A1
Physics

Bit vector gather row count calculation and handling in direct memory access engine

#15 | 2018-04-12
US20180101530A1
Physics

Dynamically configurable high performance database-aware hash engine

#16 | 2018-03-08
US20180067889A1
Physics

Processor core to coprocessor interface with FIFO semantics

#17 | 2017-09-21
US20170270053A1
Physics

Run length encoding aware direct memory access filtering engine for scratchpad enabled multicore processors

#18 | 2017-09-21
US20170270052A1
Physics

Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors

#19 | 2017-03-23
US20170083257A1
Physics

Distributed shared memory using interconnected atomic transaction engines at respective memory interfaces

InventorID:

1831568 ⎘