Gresham, Oregon
United States
32
2025-05-08
The entities that hold a legal rights for patent applications filed by inventor PRICE David T.:
David T. PRICE from Gresham, US has applied for patents for these inventions. The list has both pending applications and granted patents:
EDGE SEALS FOR SEMICONDUCTOR PACKAGES
#2 | 2025-04-17ARC PREVENTION FOR BONDED WAFERS OF A CHIP STACK
#3 | 2024-11-21GLOBAL SHUTTER SENSOR SYSTEMS AND RELATED METHODS
#4 | 2024-11-07CHIP STACKING WITH BOND PAD ABOVE A BONDLINE
#5 | 2024-09-26Semiconductor devices with single-photon avalanche diodes and isolation structures
#6 | 2024-06-13Edge seals for semiconductor packages
#7 | 2024-05-02IMPROVED SEALS FOR SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODE PIXELS
#8 | 2023-11-02METHOD AND APPARATUS RELATED TO CONTROLLABLE THIN FILM RESISTORS FOR ANALOG INTEGRATED CIRCUITS
#9 | 2023-11-02BACKSIDE ILLUMINATION IMAGE SENSORS
#10 | 2023-08-17Edge seals for semiconductor packages
#11 | 2022-11-17Semiconductor devices with single-photon avalanche diodes and isolation structures
#12 | 2022-08-25METHOD AND APPARATUS RELATED TO CONTROLLABLE THIN FILM RESISTORS FOR ANALOG INTEGRATED CIRCUITS
#13 | 2022-06-09FIN TRANSISTORS WITH SEMICONDUCTOR SPACERS
#14 | 2022-03-24Global shutter sensor systems and related methods
#15 | 2022-01-06Method of forming a semiconductor device
#16 | 2021-04-15Stacked transistor assembly with dual middle mounting clips
#17 | 2020-10-15METAL INSULATOR METAL (MIM) CAPACITORS
#18 | 2020-08-27IMAGE SENSOR DEVICES AND RELATED METHODS
#19 | 2019-12-26Backside illumination image sensors
#20 | 2019-11-28Edge seals for semiconductor packages
#21 | 2019-02-07Stacked image sensor capacitors and related methods
#22 | 2018-10-02Stacked image sensor capacitors and related methods
#23 | 2018-08-02Edge seals for semiconductor packages
#24 | 2017-03-30Semiconductor image sensor structure having metal-filled trench contact
#25 | 2017-02-14Method for forming a semiconductor image sensor device
#26 | 2008-06-05Method for redirecting void diffusion away from vias in an integrated circuit design
#27 | 2008-05-01Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes
#28 | 2007-11-08Method and apparatus for diverting void diffusion in integrated circuit conductors
#29 | 2007-07-05Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design
#30 | 2007-05-31Methods of memory bitmap verification for finished product
#31 | 2007-04-12Method for SRAM bitmap verification
#32 | 2005-09-01Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes
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