Milpitas, California
United States
30
2024-12-12
The entities that hold a legal rights for patent applications filed by inventor Yu Jixin:
Jixin Yu from Milpitas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY DEVICE INCLUDING WORD LINE CONTACT STRIPS AND METHODS OF FORMING THE SAME
#2 | 2024-11-21THREE-DIMENSIONAL MEMORY DEVICE INCLUDING TRENCH BRIDGE STRUCTURES HAVING DIFFERENT VOLUMES AND METHODS OF FORMING THE SAME
#3 | 2024-10-03THREE-DIMENSIONAL MEMORY DEVICE CONTAINING COMPOSITE DIELECTRIC ISOLATION STRUCTURE IN A STAIRCASE REGION AND METHODS OF FORMING THE SAME
#4 | 2024-08-29THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-LEVEL WORD LINE CONTACT WELLS AND METHODS FOR MANUFACTURING THE SAME
#5 | 2024-07-25THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF INCLUDING EXPANDED SUPPORT OPENINGS AND DOUBLE SPACER WORD LINE CONTACT FORMATION
#6 | 2024-07-25THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF INCLUDING EXPANDED SUPPORT OPENINGS AND DOUBLE SPACER WORD LINE CONTACT FORMATION
#7 | 2022-11-03Three-dimensional memory device with finned support pillar structures and method of forming the same
#8 | 2022-06-09Three-dimensional memory device including backside trench support structures and methods of forming the same
#9 | 2021-01-28Three-dimensional memory device including self-aligned dielectric isolation regions for connection via structures and method of making the same
#10 | 2020-10-01Three-dimensional memory device containing asymmetric, different size support pillars and method for making the same
#11 | 2020-10-01Memory die containing stress reducing backside contact via structures and method of making the same
#12 | 2020-09-17Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same
#13 | 2020-05-19Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same
#14 | 2020-02-27Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same
#15 | 2018-09-13Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#16 | 2018-07-12Three-dimensional memory device with enhanced mechanical stability semiconductor pedestal and method of making thereof
#17 | 2018-05-03Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#18 | 2018-05-03Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#19 | 2018-05-03Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#20 | 2017-12-14Method of forming a staircase in a semiconductor device using a linear alignment control feature
#21 | 2017-12-14Within-array through-memory-level via structures and method of making thereof
#22 | 2017-12-07Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
#23 | 2017-08-24Three dimensional memory device containing discrete silicon nitride charge storage regions
#24 | 2017-08-17Self-aligned isolation dielectric structures for a three-dimensional memory device
#25 | 2017-08-17Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
#26 | 2017-08-10Multi-tier replacement memory stack structure integration scheme
#27 | 2017-06-22Through-memory-level via structures for a three-dimensional memory device
#28 | 2017-06-22Through-memory-level via structures for a three-dimensional memory device
#29 | 2017-06-22Through-memory-level via structures for a three-dimensional memory device
#30 | 2017-06-06Three dimensional memory device with peripheral devices under dummy dielectric layer stack and method of making thereof
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