Robert Seidel

Semiconductor structure with substantially straight contact profile

SEMICONDUCTOR STRUCTURE WITH SUBSTANTIALLY STRAIGHT CONTACT PROFILE

Embedded metal-insulator-metal capacitor

Method of forming an embedded metal-insulator-metal (MIM) capacitor

Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes

TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS

Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process

Metallization system of a semiconductor device comprising rounded interconnects formed by hard mask rounding

Contact elements of semiconductor devices comprising a continuous transition to metal lines of a metallization layer

Contact elements of semiconductor devices formed on the basis of a partially applied activation layer

Nano imprint technique with increased flexibility with respect to alignment and feature shaping

Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material

Technique for compensating for a difference in deposition behavior in an interlayer dielectric material

Microstructure device including a metallization structure with self-aligned air gaps and refilled air gap exclusion zones

Microstructure device including a metallization structure with self-aligned air gaps between closely spaced metal lines

REDUCING LEAKAGE AND DIELECTRIC BREAKDOWN IN DIELECTRIC MATERIALS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY FORMING RECESSES

Semiconductor device comprising a carbon-based material for through hole vias

Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors

Metal cap layer of increased electrode potential for copper-based metal regions in semiconductor devices

Electrical circuit with a nanostructure and method for producing a contact connection of a nanostructure

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME

Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process

Technique for compensating for a difference in deposition behavior in an interlayer dielectric material

Method for fabricating a nanoelement field effect transistor with surrounded gate structure

Semiconductor power switch having nanowires

SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME

Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices

METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY ELECTROLESS DEPOSITION USING A SELECTIVELY PROVIDED ACTIVATION LAYER

Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime

METHOD FOR INCREASING THE PLANARITY OF A SURFACE TOPOGRAPHY IN A MICROSTRUCTURE

Nano imprint technique with increased flexibility with respect to alignment and feature shaping

Method for fabricating a nanoelement field effect transistor with surrounded gate structure

Integrated electronic component