Mountain View, California
United States
34
2016-05-05
The entities that hold a legal rights for patent applications filed by inventor Liu Kai:
Kai Liu from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
#2 | 2015-08-27Embedded die redistribution layers for active device
#3 | 2015-03-19POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD
#4 | 2014-06-05Method for top-side cooled semiconductor package with stacked interconnection plates
#5 | 2014-04-17Dual-leadframe multi-chip package
#6 | 2014-03-20Semiconductor packaging method using connecting plate for internal connection
#7 | 2014-03-13Semiconductor package with connecting plate for internal connection
#8 | 2014-02-27Stacked dual chip package having leveling projections
#9 | 2014-02-06Top exposed semiconductor chip package
#10 | 2013-11-14Multi-layer lead frame package and method of fabrication
#11 | 2013-07-18Package leadframe for dual side assembly
#12 | 2013-04-25Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method
#13 | 2012-11-15Method for making solder-top enhanced semiconductor device of low parasitic packaging impedance
#14 | 2012-06-28Dual-leadframe multi-chip package and method of manufacture
#15 | 2012-02-09Compact semiconductor package with integrated bypass capacitor
#16 | 2011-09-29Dual-leadframe multi-chip package and method of manufacture
#17 | 2011-09-22Stacked dual chip package and method of fabrication
#18 | 2011-09-22Multi-layer lead frame package and method of fabrication
#19 | 2011-09-15Semiconductor packaging and fabrication method using connecting plate for internal connection
#20 | 2011-03-24Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
#21 | 2010-12-09Power semiconductor device package and fabrication method
#22 | 2010-10-28Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates
#23 | 2010-06-03Compact semiconductor package with integrated bypass capacitor and method
#24 | 2010-06-03Top-side cooled semiconductor package with stacked interconnection plates and method
#25 | 2010-03-25Top exposed clip with window array
#26 | 2010-02-11Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates
#27 | 2009-12-03Conductive clip for semiconductor device package
#28 | 2009-09-24Semiconductor package having a bridged plate interconnection
#29 | 2009-09-17Dual flat non-leaded semiconductor package
#30 | 2009-09-03Semiconductor package having a bridge plate connection
#31 | 2009-04-30Solder-top enhanced semiconductor device for low parasitic impedance packaging
#32 | 2009-03-05CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION
#33 | 2008-04-17Semiconductor package having a bridged plate interconnection
#34 | 2007-12-20Semiconductor package having dimpled plate interconnections
205310 ⎘