Inventor profile of:

Bin He

City:

Orlando, Florida

Country:

United States

Published Applications:

21

Last publication date:

2025-04-24

Top Assignees for applications by Bin He

The entities that hold a legal rights for patent applications filed by inventor He Bin:

Recent patent applications by He Bin

Bin He from Orlando, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-04-24
US20250130794A1
Physics

MULTI-FORMAT OPERAND CIRCUIT

#2 | 2025-04-24
US20250130774A1
Physics

FLOATING POINT BIAS SWITCHING

#3 | 2025-04-24
US20250130769A1
Physics

STOCHASTIC ROUNDING CIRCUIT

#4 | 2025-04-24
US20250130767A1
Physics

FLOATING-POINT CONVERSION CIRCUIT

#5 | 2024-05-23
US20240168719A1
Physics

Dual vector arithmetic logic unit

#6 | 2024-05-02
US20240143283A1
Physics

Processing unit with small footprint arithmetic logic unit

#7 | 2024-04-04
US20240111530A1
Physics

MATRIX MULTIPLICATION UNIT WITH FLEXIBLE PRECISION OPERATIONS

#8 | 2023-03-30
US20230097279A1
Physics

CONVOLUTIONAL NEURAL NETWORK OPERATIONS

#9 | 2022-06-16
US20220188076A1
Physics

Dual vector arithmetic logic unit

#10 | 2022-06-02
US20220171621A1
Physics

Arithmetic logic unit register sequencing

#11 | 2021-12-30
US20210405968A1
Physics

Processing unit with small footprint arithmetic logic unit

#12 | 2021-05-27
US20210157588A1
Physics

Dedicated vector sub-processor system

#13 | 2021-05-27
US20210157581A1
Physics

Arithemetic logic unit register sequencing

#14 | 2021-04-01
US20210096877A1
Physics

COLLAPSING BUBBLES IN A PROCESSING UNIT PIPELINE

#15 | 2021-03-25
US20210089304A1
Physics

Matrix multiplication unit with flexible precision operations

#16 | 2020-09-17
US20200293329A1
Physics

Pipeline including separate hardware data paths for different instruction types

#17 | 2020-09-17
US20200293286A1
Physics

Processing unit with mixed precision operations

#18 | 2018-05-03
US20180121386A1
Physics

SUPER SINGLE INSTRUCTION MULTIPLE DATA (SUPER-SIMD) FOR GRAPHICS PROCESSING UNIT (GPU) COMPUTING

#19 | 2018-04-26
US20180113714A1
Physics

Pipeline including separate hardware data paths for different instruction types

#20 | 2018-04-26
US20180113709A1
Physics

Pairing SIMD lanes to perform double precision operations

#21 | 2017-12-28
US20170371393A1
Physics

Method and processing apparatus for gating redundant threads

InventorID:

2076417 ⎘