Campbell, California
United States
45
2026-02-26
The entities that hold a legal rights for patent applications filed by inventor Plants William C.:
William C. Plants from Campbell, US has applied for patents for these inventions. The list has both pending applications and granted patents:
DIRECT-BONDED NATIVE INTERCONNECTS AND ACTIVE BASE DIE
#2 | 2024-08-08Direct-Bonded Native Interconnects And Active Base Die
#3 | 2022-07-28Direct-bonded native interconnects and active base die
#4 | 2020-11-12Direct-bonded native interconnects and active base die
#5 | 2020-06-18Direct-bonded native interconnects and active base die
#6 | 2019-01-10Enhanced memory reliability in stacked memory devices
#7 | 2018-08-16Preferred state encoding in non-volatile memories
#8 | 2018-06-28Wafer testing without direct probing
#9 | 2018-06-21Self healing compute array
#10 | 2018-05-03Enhanced memory reliability in stacked memory devices
#11 | 2018-04-26DRAM adjacent row disturb mitigation
#12 | 2018-04-12Direct-bonded native interconnects and active base die
#13 | 2018-01-25FPGA RAM blocks optimized for use as register files
#14 | 2017-10-03Enhanced memory reliability in stacked memory devices
#15 | 2017-04-27DRAM adjacent row disturb mitigation
#16 | 2016-10-27Preferred state encoding in non-volatile memories
#17 | 2016-06-30Retention optimized memory device using predictive data inversion
#18 | 2015-07-30Retention optimized memory device using predictive data inversion
#19 | 2014-10-23Retention optimized memory device using predictive data inversion
#20 | 2013-10-17FPGA RAM blocks optimized for use as register files
#21 | 2013-05-02Common doped region with separate gate control for a logic compatible non-volatile memory cell
#22 | 2012-11-08FPGA RAM blocks optimized for use as register files
#23 | 2010-06-24Programmable delay line compensated for process, voltage, and temperature
#24 | 2010-06-03Programmable logic device with a microcontroller-based control system
#25 | 2010-04-22Flexible carry scheme for field programmable gate arrays
#26 | 2010-04-20Programmable delay line compensated for process, voltage, and temperature
#27 | 2010-03-23Programmable logic device with a microcontroller-based control system
#28 | 2010-02-18Non-volatile two-transistor programmable logic cell and array layout
#29 | 2010-02-16Flexible carry scheme for field programmable gate arrays
#30 | 2010-01-21Flash-based FPGA with secure reprogramming
#31 | 2009-08-27Non-volatile two-transistor programmable logic cell and array layout
#32 | 2009-08-11Non-volatile two-transistor programmable logic cell and array layout
#33 | 2009-05-26Non-volatile two-transistor programmable logic cell and array layout
#34 | 2009-05-26Non-volatile two-transistor programmable logic cell and array layout
#35 | 2009-04-09Delay locked loop for an FPGA architecture
#36 | 2009-01-27Delay locked loop for an FPGA architecture
#37 | 2009-01-06Non-volatile two-transistor programmable logic cell and array layout
#38 | 2008-10-30SRAM cell controlled by flash memory cell
#39 | 2008-08-14ARCHITECTURE FOR FACE-TO-FACE BONDING BETWEEN SUBSTRATE AND MULTIPLE DAUGHTER CHIPS
#40 | 2008-04-15Architecture for face-to-face bonding between substrate and multiple daughter chips
#41 | 2007-08-16SRAM cell controlled by flash memory cell
#42 | 2007-05-29SRAM cell controlled by flash memory cell
#43 | 2007-01-30Delay locked loop for and FPGA architecture
#44 | 2006-08-29SRAM cell controlled by non-volatile memory cell
#45 | 2005-12-13Delay locked loop for an FPGA architecture
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