San Jose, California
United States
21
2025-02-06
21
2025-11-18
These are the the leading inventors for applications assigned to Adeia Semiconductor Inc.:
Adeia Semiconductor Inc. based in San Jose, US has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
3D NAND - HIGH ASPECT RATIO STRINGS AND CHANNELS
#2 | 2024-09-19 ✅ Patent 12,278,215 granted on 2025-04-15Integrated voltage regulator and passive components
#3 | 2024-08-08 ✅ Patent 12,293,993 granted on 2025-05-063D chip sharing data bus
#4 | 2024-08-08 ✅ Patent 12,362,182 granted on 2025-07-15Direct-Bonded Native Interconnects And Active Base Die
#5 | 2024-07-11 ✅ Patent 12,218,059 granted on 2025-02-04Stacked IC structure with orthogonal interconnect layers
#6 | 2024-06-13 ✅ Patent 12,532,594 granted on 2026-01-20Monolithic Segmented LED Array Architecture With Islanded Epitaxial Growth
#7 | 2024-05-09 ✅ Patent 12,248,869 granted on 2025-03-11Three dimensional circuit implementing machine trained network
#8 | 2023-05-04 ✅ Patent 12,272,730 granted on 2025-04-08Transistor level interconnection methodologies utilizing 3D interconnects
#9 | 2023-05-04 ✅ Patent 12,142,528 granted on 2024-11-123D chip with shared clock distribution network
#10 | 2023-03-23 ✅ Patent 11,894,345 granted on 2024-02-06Integrated voltage regulator and passive components
#11 | 2022-10-13 ✅ Patent 12,035,529 granted on 2024-07-093D NAND—high aspect ratio strings and channels
#12 | 2022-04-07 ✅ Patent 11,790,219 granted on 2023-10-17Three dimensional circuit implementing machine trained network
#13 | 2022-03-03 ✅ Patent 12,401,010 granted on 2025-08-263D PROCESSOR
#14 | 2021-08-12 ✅ Patent 11,862,604 granted on 2024-01-02Systems and methods for releveled bump planes for chiplets
#15 | 2021-07-15 ✅ Patent 11,688,776 granted on 2023-06-27Transistor level interconnection methodologies utilizing 3D interconnects
#16 | 2021-07-01 ✅ Patent 11,881,454 granted on 2024-01-23Stacked IC structure with orthogonal interconnect layers
#17 | 2021-06-03 ✅ Patent 12,074,092 granted on 2024-08-27Hard IP blocks with physically bidirectional passageways
#18 | 2021-04-08 ✅ Patent 11,557,516 granted on 2023-01-173D chip with shared clock distribution network
#19 | 2020-12-24 ✅ Patent 11,916,076 granted on 2024-02-27Device disaggregation for improved performance
#20 | 2020-03-12 ✅ Patent 11,914,148 granted on 2024-02-27Stacked optical waveguides
#21 | 2020-03-05 ✅ Patent 11,515,291 granted on 2022-11-29Integrated voltage regulator and passive components
Also check out ADEIA SEMICONDUCTOR INC.'s (San Jose, United States) applicant profile with 33 patent applications submitted.
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