Veeraraghavan S. BASKER

FINFET DEVICES

ISOLATION MODULE FOR BACKSIDE POWER DELIVERY IN DEVICES WITHOUT INNER SPACERS

SELECTIVE REMOVAL OF SEMICONDUCTOR FINS

BACKSIDE POWER DELIVERY IN DEVICES WITHOUT INNER SPACERS

SELECTIVE PROCESS FOR SIMULTANEOUS PFET EPI HARDMASK AND NFET PARTIAL BOTTOM DIELECTRIC ISOLATION LAYER FORMATION

ISOLATION MODULE FOR BACKSIDE POWER DELIVERY

DIRECT NITRATION FOR BACKSIDE POWER DELIVER NETWORK ISOLATION MODULE

SELF-ALIGNING BACKSIDE GATE CONNECTION

ISOLATION MODULE FOR BACKSIDE POWER DELIVERY

ISOLATION MODULE FOR BACKSIDE POWER DELIVERY

FINFET DEVICES

ENHANCED LINERLESS VIAS

SEMICONDUCTOR DEVICE HAVING REDUCED CONTACT RESISTANCE

REDUCED DIFFUSION BREAK STRUCTURE

NARROWING SINGLE DIFFUSION BREAK

GATE-ALL-AROUND FIELD-EFFECT-TRANSISTOR WITH WRAP-AROUND-CHANNEL INNER SPACER

CO-INTEGRATING GATE-ALL-AROUND NANOSHEET TRANSISTORS AND COMB NANOSHEET TRANSISTORS

WRAPAROUND CONTACT WITH REDUCED DISTANCE TO CHANNEL

Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages

HIGH-DENSITY METAL-INSULATOR-METAL CAPACITOR INTEGRATION WTH NANOSHEET STACK TECHNOLOGY

Co-integrated logic, electrostatic discharge, and well contact devices on a substrate

INTEGRATING GATE-CUTS AND SINGLE DIFFUSION BREAK ISOLATION POST-RMG USING LOW-TEMPERATURE PROTECTIVE LINERS

Gate-all-around field effect transistor with bottom dielectric isolation

SEMICONDUCTOR DEVICE HAVING HYBRID MIDDLE OF LINE CONTACTS

Electrostatic discharge diode having dielectric isolation layer

Bottom Air Spacer by Oxidation

Late replacement bottom isolation for nanosheet devices

Vertical FET replacement gate formation with variable fin pitch

Semiconductor structures with backside gate contacts

Integrated nanosheet field effect transistors and floating gate memory cells

Field effect transistors with bottom dielectric isolation

STACKED FET WITH DIFFERENT CHANNEL MATERIALS

Thick gate oxide device option for nanosheet device

Gate-all-around nanosheet field effect transistor integrated with fin field effect transistor

Hybrid diffusion break with EUV gate patterning

FORMATION OF TRENCH SILICIDE SOURCE OR DRAIN CONTACTS WITHOUT GATE DAMAGE

SELECTIVE REMOVAL OF SEMICONDUCTOR FINS

Gate-all-around devices with isolated and non-isolated epitaxy regions for strain engineering

Co-integration of gate-all-around FET, FINFET and passive devices on bulk substrate

Wraparound contact to a buried power rail

Field effect transistor

Wrap around contact process margin improvement with early contact cut

FinFET devices

Dual step etch-back inner spacer formation

Protective bilayer inner spacer for nanosheet devices

Self-aligned isolation for nanosheet transistor

Nanosheet semiconductor devices with sigma shaped inner spacer

Wrap around contact process margin improvement with early contact cut

Nanosheet device with tall suspension and tight contacted gate poly-pitch

Nanosheet transistor device with bottom isolation

Dual step etch-back inner spacer formation

Protective bilayer inner spacer for nanosheet devices

Two-dimensional (2D) self-aligned contact (or via) to enable further device scaling

Method and structure of metal cut

Self-aligned gate isolation with asymmetric cut placement

Transistor having reduced contact resistance

Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor

FinFET devices

Source and drain EPI protective spacer during single diffusion break formation

Electrical isolation for nanosheet transistor devices

Vertical field effect transistor with top and bottom airgap spacers

Source/drain contact depth control

Semiconductor device with mitigated local layout effects

Source and drain contact cut last process to enable wrap-around-contact

Source and drain contact cut last process to enable wrap-around-contact

Formation of trench silicide source or drain contacts without gate damage

Structure to enable titanium contact liner on pFET source/drain regions

Self-aligned wrap-around trench contacts

Replacement metal gate structures

Vertical FET with shaped spacer to reduce parasitic capacitance

Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects

Fin isolation to mitigate local layout effects

Dual silicide liner flow for enabling low contact resistance

Selective removal of semiconductor fins

Replacement metal gate structures

Replacement metal gate structures

Transistor with recessed cross couple for gate contact over active region integration

Embedded source/drain structure for tall FinFet and method of formation

Interface-less contacts to source/drain regions and gate electrode over active portion of device

Metal-insulator-metal capacitor structure

Nanosheet device with close source drain proximity

Electrical fuse and/or resistor structures

Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains

Vertical transport FET devices having air gap top spacer

Metal-insulator-metal capacitor structure

Electrical fuse and/or resistor structures

Semiconductor device including dual trench epitaxial dual-liner contacts

FINFET WITH REDUCED PARASITIC CAPACITANCE

EMBEDDED SOURCE/DRAIN STRUCTURE FOR TALL FINFET AND METHOD OF FORMATION

Metal-insulator-metal capacitor structure

Replacement metal gate structures

Capacitors

SiGe FINS FORMED ON A SUBSTRATE

SiGe FINS FORMED ON A SUBSTRATE

Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains

Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains

Forming a fin using double trench epitaxy

Nanosheet device with close source drain proximity

Replacement metal gate structures

Vertical FET with shaped spacer to reduce parasitic capacitance