Nhan Do

DUAL READ MODE NON-VOLATILE MEMORY SEMICONDUCTOR DEVICE

ALGORITHMS FOR UPDATING SOFTWARE CODE IN FLASH MEMORY DURING SYSTEM OPERATION

SELF-ALIGNED METHOD OF FORMING EEPROM CELLS

SPLIT-GATE NON-VOLATILE MEMORY ARRAY WITH BIDIRECTIONAL OPERATION

METHOD OF FORMING RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS

ARRAY OF MULTI-VALUE NON-VOLATILE MEMORY CELLS

SEMICONDUCTOR DEVICE AND METHOD WITH MEMORY CELLS HAVING COUPLING GATE SELF-ALIGNED TO FLOATING GATE

SEMICONDUCTOR DEVICE WITH NON-PLANAR MOSFET DEVICE DIE AND PLANAR MOSFET DEVICE DIE

NON-VOLATILE MEMORY CELL WITH ONO COMPOUND INSULATION LAYER BETWEEN FLOATING AND CONTROL GATES AND A METHOD OF FABRICATION

PROGRAMMABLE LOGIC BLOCK COMPRISING FLASH MEMORY ARRAY TO STORE CONFIGURATION DATA FOR PROGRAMMABLE LOGIC

METHOD OF MAKING MEMORY CELLS, TRANSISTOR DEVICES AND LOGIC DEVICES ON SILICON-ON-INSULATOR SUBSTRATE

LOW VOLTAGE RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS AND METHOD OF FORMATION

PROGRAMMING OF ANALOG NON-VOLATILE MEMORY CELL IN NEURAL NETWORK

Memory Device Formed On Silicon-On-Insulator Substrate, And Method Of Making Same

Verifying Or Reading A Cell In An Analog Neural Memory In A Deep Learning Artificial Neural Network

ERASING OF A WORD OR A PAGE OF NON-VOLATILE MEMORY CELLS IN AN ANALOG NEURAL MEMORY SYSTEM

Neural network classifier using array of three-gate non-volatile memory cells

SEMICONDUCTOR DEVICE WITH COMMUNICATION RING

NEURAL NETWORK CLASSIFIER USING ARRAY OF THREE-GATE NON-VOLATILE MEMORY CELLS

Neural network classifier using array of three-gate non-volatile memory cells

Memory cell array with row direction gap between erase gate lines and dummy floating gates

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

Programming of a Selected Non-volatile Memory Cell by Changing Programming Pulse Characteristics

VOLTAGE GENERATOR FOR ANALOG NEURAL MEMORY ARRAY

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM

Output circuit

Neural network array comprising one or more coarse cells and one or more fine cells

PROGRAMMING OF A SELECTED NON-VOLATILE MEMORY CELL

ARTIFICIAL NEURAL NETWORK COMPRISING REFERENCE ARRAY FOR I-V SLOPE CONFIGURATION

ARTIFICIAL NEURAL NETWORK COMPRISING A THREE-DIMENSIONAL INTEGRATED CIRCUIT

Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate

METHOD OF FORMING A DEVICE WITH PLANAR SPLIT GATE NON-VOLATILE MEMORY CELLS, PLANAR HV DEVICES, AND FINFET LOGIC DEVICES ON A SUBSTRATE

Setting levels for a programming operation in a neural network array

Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate using a dummy area

MEMORY DEVICE OF NON-VOLATILE MEMORY CELLS

Method Of Scanning An Image Using Non-volatile Memory Array Neural Network Classifier

METHOD OF FORMING PAIRS OF THREE-GATE NON-VOLATILE FLASH MEMORY CELLS USING TWO POLYSILICON DEPOSITION STEPS

Summing circuit for neural network

Output circuitry for non-volatile memory array in neural network

Neural network classifier using array of three-gate non-volatile memory cells

Verification of a weight stored in a non-volatile memory cell in a neural network following a programming operation

SPLIT GATE NON-VOLATILE MEMORY CELLS, HV AND LOGIC DEVICES WITH FINFET STRUCTURES, AND METHOD OF MAKING SAME

Method of determining defective die containing non-volatile memory cells

Input function circuit block and output neuron circuit block coupled to a vector-by-matrix multiplication array in an artificial neural network

Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network

Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network

Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network

Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network

PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

NON-VOLATILE MEMORY CELL ARRAY FORMED IN A P-WELL IN A DEEP N-WELL IN A P-SUBSTRATE

Precise data tuning method and apparatus for analog neural memory in an artificial neural network

ULTRA-PRECISE TUNING OF NEURAL MEMORY CELLS

Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system

Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system

Virtual ground non-volatile memory array

Testing of analog neural memory cells in an artificial neural network

Compensation for leakage in an array of analog neural memory cells in an artificial neural network

Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same

Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate

Programming analog neural memory cells in deep learning artificial neural network

Method of forming a device with split gate non-volatile memory cells, HV devices having planar channel regions and FINFET logic devices

Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates

Architectures for storing and retrieving system data in a non-volatile memory system

Deep learning neural network classifier using non-volatile memory array

SPLIT GATE NON-VOLATILE MEMORY CELLS, HV AND LOGIC DEVICES WITH FINFET STRUCTURES, AND METHOD OF MAKING SAME

Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same

Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same

Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and FinFET logic devices

Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks

Method of forming split gate memory cells with thinner tunnel oxide

Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network

Neural network classifier using array of three-gate non-volatile memory cells

Method of forming split gate memory cells with thinned side edge tunnel oxide

Method of making memory cells, high voltage devices and logic devices on a substrate

Analog neural memory array in artificial neural network comprising logical cells and improved programming mechanism

Non-volatile memory system using strap cells in source line pull down circuits

FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling

Precision tuning of a page or word of non-volatile memory cells and associated high voltage circuits for an analog neural memory array in an artificial neural network

Output circuitry for non-volatile memory array in neural network

Method of forming a device with FinFET split gate non-volatile memory cells and FinFET logic devices

Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network

Programming analog neural memory cells in deep learning artificial neural network

Set-while-verify circuit and reset-while verify circuit for resistive random access memory cells

Verification of a weight stored in a non-volatile memory cell in a neural network following a programming operation

Precise data tuning method and apparatus for analog neural memory in an artificial neural network

Circuitry to compensate for data drift in analog neural memory in an artificial neural network

Precise data tuning method and apparatus for analog neural memory in an artificial neural network

Method Of Forming A Device With Split Gate Non-volatile Memory Cells, HV Devices Having Planar Channel Regions And FINFET Logic Devices

Virtual ground non-volatile memory array

Output circuits for an analog neural memory system for deep learning neural network

Verifying or reading a cell in an analog neural memory in a deep learning artificial neural network

Precise programming method and apparatus for analog neural memory in an artificial neural network

Four gate, split-gate flash memory array with byte erase operation

Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network

Temperature compensation in an analog memory array by changing a threshold voltage of a selected memory cell in the array

Precision tuning for the programming of analog neural memory in a deep learning artificial neural network

Testing circuitry and methods for analog neural memory in artificial neural network

Testing circuitry and methods for analog neural memory in artificial neural network

Method of forming split gate memory cells