Inventor profile of:

Peter B. Gillingham

City:

Kanata

Country:

Canada

Published Applications:

19

Last publication date:

2014-04-17

Top Assignees for applications by Peter B. Gillingham

The entities that hold a legal rights for patent applications filed by inventor Gillingham Peter B.:

Recent patent applications by Gillingham Peter B.

Peter B. Gillingham from Kanata, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2014-04-17
US20140104969A1
Physics

Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory

#2 | 2013-09-26
US20130249592A1
Electricity

TERMINATION CIRCUIT FOR ON-DIE TERMINATION

#3 | 2013-05-16
US20130121096A1
Electricity

Delay locked loop implementation in a synchronous dynamic random access memory

#4 | 2012-05-24
US20120127798A1
Physics

Method and apparatus for sharing internal power supplies in integrated circuit devices

#5 | 2012-03-08
US20120056335A1
Electricity

Multi-chip package with offset die stacking

#6 | 2011-12-29
US20110317704A1
Electricity

DENSE MODE CODING SCHEME

#7 | 2011-03-03
US20110050320A1
Electricity

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

#8 | 2010-06-24
US20100162053A1
Physics

Error detection method and a system including one or more memory devices

#9 | 2010-05-06
US20100115172A1
Physics

BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER

#10 | 2010-02-25
US20100049870A1
Electricity

Dense mode coding scheme

#11 | 2009-12-24
US20090316514A1
Electricity

Delay locked loop implementation in a synchronous dynamic random access memory

#12 | 2009-02-12
US20090039927A1
Physics

Clock mode determination in a memory system

#13 | 2008-05-01
US20080101372A1
Electricity

Dense mode coding scheme

#14 | 2008-03-18
US10262643
-

Dense mode coding scheme

#15 | 2007-08-30
US20070200611A1
Physics

DRAM boosted voltage supply

#16 | 2006-02-09
US20060028899A1
Physics

DRAM boosted voltage supply

#17 | 2006-01-31
US10645330
-

Delay locked loop implementation in a synchronous dynamic random access memory

#18 | 2005-12-27
US10463218
-

DRAM boosted voltage supply

#19 | 2005-12-01
US20050265506A1
Electricity

Delay locked loop implementation in a synchronous dynamic random access memory

InventorID:

244995 ⎘