MOSAID TECHNOLOGIES INCORPORATED

Clock mode determination in a memory system

Clock mode determination in a memory system

Structure and method for providing line end extensions for fin-type active regions

NAND flash memory with vertical cell stack structure and method for manufacturing same

Non-volatile memory device with concurrent bank operations

Clock mode determination in a memory system

Structure and method for providing line end extensions for fin-type active regions

NAND flash memory with vertical cell stack structure and method for manufacturing same

Non-volatile memory device with concurrent bank operations

Clock mode determination in a memory system

Power managers for an integrated circuit

NAND flash memory with vertical cell stack structure and method for manufacturing same

Flash memory system

Scheduling systems and methods for wireless networks

Relay systems and methods for wireless networks

Vertical gate stacked NAND and row decoder for erase operation

U-shaped common-body type cell string

Lithography-friendly local read circuit for NAND flash memory devices and manufacturing method thereof

Nonvolatile memory with split substrate select gates and hierarchical bitline configuration

Flash multi-level threshold distribution scheme

NAND flash memory with vertical cell stack structure and method for manufacturing same

Frequency division multiplexing system with selectable rate

Clock mode determination in a memory system

Memory with output control

Method and system for programming non-volatile memory with junctionless cells

Non-volatile memory device having configurable page size

PLL locking control in daisy chained memory system

Method and system for packet processing

Method, apparatus, signals and media, for selecting operating conditions of a genset

Ring-of-clusters network topologies

Integrated erase voltage path for multiple cell substrates in nonvolatile memory devices

Network architecture for data communication

Non-volatile semiconductor memory having multiple external power supplies

Split block decoder for a nonvolatile memory device

System and method providing interoperability between cellular and other wireless systems

Method and apparatus for reducing pool starvation in a shared memory switch

Semiconductor memory asynchronous pipeline

Flash memory controller having dual mode pin-out

Memory system having a plurality of serially connected devices

NAND flash memory having multiple cell substrates

Bridging device having a configurable virtual page size

Dual function compatible non-volatile memory device

Non-volatile memory with dynamic multi-mode operation

Frequency-doubling delay locked loop

Phase change memory word line driver

Configurable module and memory subsystem

Telephone communication system and method over local area network wiring

Multi-chip package with offset die stacking and method of making same

Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage

Memory controller with flexible data alignment to clock

Flash multi-level threshold distribution scheme

Clock mode determination in a memory system

Error detection and correction codes for channels and memories with incomplete error characteristics

Memory with output control

Local area network of serial intelligent cells

Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance

Modular outlet

Congestion management in a network

Single-strobe operation of memory devices

Semiconductor device having metal lines with slits

Method and apparatus for connecting memory dies to form a memory system

Method and system for accessing a flash memory device

Device selection schemes in multi chip package NAND flash memory system

Delay locked loop circuit and method

Scalable memory system

Multiple-bit per cell (MBC) non-volatile memory apparatus and system having polarity control and method of programming same

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

Solid state drive memory system

Non-volatile memory with dynamic multi-mode operation

CPU with stacked memory

Telephone outlet for implementing a local area network over telephone lines and a local area network using such outlets