Mosaid Technologies Incorporated

Wide frequency range delay locked loop

Flash multi-level threshold distribution scheme

Clock mode determination in a memory system

Memory with output control

Modular outlet

Delay locked loop circuit and method

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

Non-volatile memory with dynamic multi-mode operation

High bandwidth memory interface

Non-volatile memory device having configurable page size

Delay locked loop implementation in a synchronous dynamic random access memory

Apparatus and method for producing device identifiers for serially interconnected devices of mixed type

Method, apparatus, signals and media, for selecting operating conditions of a genset

Method of configuring non-volatile memory for a hybrid disk drive

Apparatus and method for producing IDs for interconnected devices of mixed type

Double data rate output circuit

Frequency-doubling delay locked loop

Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh

Memory device and method for repairing a semiconductor memory

Wide frequency range delay locked loop

Embedded memory databus architecture

Dual function compatible non-volatile memory device

Multi-level cell access buffer with dual function

Telephone communication system over a single telephone line

Initialization circuit for delay locked loop

Source side asymmetrical precharge programming scheme

Non-volatile semiconductor memory with page erase

Trunking in a matrix

Memory with output control

Circuit for clamping current in a charge pump

Local area network for distributing data communication, sensing and control signals

Voltage down converter for high speed memory

Data flow control in multiple independent port

Frequency division multiplexing system with selectable rate

Non-volatile semiconductor memory device with power saving feature

Semiconductor memory asynchronous pipeline

Bridge device architecture for connecting discrete memory devices to a system

Method and apparatus for sharing internal power supplies in integrated circuit devices

Termination circuit for on-die termination

Flexible memory operations in NAND flash devices

Charge pump for PLL/DLL

Flash multi-level threshold distribution scheme

Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance

Dynamic random access memory and boosted voltage producer therefor

Dispersion tolerant optical system and method

System for transmission line termination by signal cancellation

Multi-chip package with offset die stacking

Non-volatile memory device having configurable page size

Modular outlet

Non-volatile memory with dynamic multi-mode operation

Power supplies in flash memory devices and systems

High speed DRAM architecture with uniform access latency

Systems and methods for minimizing static leakage of an integrated circuit

Multi-chip package with thermal frame and method of assembling

Phase change memory word line driver

Apparatus and method for modeling coarse stepsize delay element and delay locked loop using same

Modular outlet

Flash memory program inhibit scheme

Multi-chip package with pillar connection

High-speed interface for daisy-chained devices

Wide frequency range delay locked loop

Non-volatile semiconductor memory with page erase

Low leakage and data retention circuitry

Memory programming using variable data width

Dual function compatible non-volatile memory device

Non-volatile memory devices and control and operation thereof

Double data rate output circuit and method

Multi-level cell access buffer with dual function

Embedded memory databus architecture

Circuit for clamping current in a charge pump

Semiconductor memory asynchronous pipeline

Source side asymmetrical precharge programming scheme

Apparatus and method for producing device identifiers for serially interconnected devices of mixed type

Dynamic random access memory with fully independent partial array refresh function

Temperature detector in an integrated circuit

NAND flash memory having multiple cell substrates

Method for stacking serially-connected integrated circuits and multi-chip device made from same

Data channel test apparatus and method thereof

System and method of operating memory devices of mixed type

Circuit and method for testing multi-device systems

Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow

Clock mode determination in a memory system

Stacked semiconductor devices including a master device

Delay locked loop circuit

Dynamic random access memory device and method for self-refreshing memory cells

Charge pump for PLL/DLL

Memory device and method for repairing a semiconductor memory

Modular outlet

Process, voltage, temperature independent switched delay compensation scheme

Reconfiguring through silicon vias in stacked multi-die packages

System and method providing interoperability between cellular and other wireless systems

Non-volatile semiconductor memory with page erase

Timing vernier using a delay locked loop

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

Communication system and method over local area network wiring

Package-level integrated circuit connection without top metal pads or bonding wire

Semiconductor memory with multiple wordline selection

Synchronous memory read data capture

Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection

Non-volatile memory bank and page buffer therefor