Inventor profile of:

Thomas Ort

City:

Veitsbronn

Country:

Germany

Published Applications:

18

Last publication date:

2025-10-02

Top Assignees for applications by Thomas Ort

The entities that hold a legal rights for patent applications filed by inventor Ort Thomas:

Recent patent applications by Ort Thomas

Thomas Ort from Veitsbronn, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-10-02
US20250309017A1
Electricity

FAN OUT PACKAGE WITH INTEGRATED PERIPHERAL DEVICES AND METHODS

#2 | 2024-10-24
US20240355697A1
Electricity

PACKAGE FORMATION METHODS INCLUDING COUPLING A MOLDED ROUTING LAYER TO AN INTEGRATED ROUTING LAYER

#3 | 2024-06-13
US20240194552A1
Electricity

FAN OUT PACKAGE WITH INTEGRATED PERIPHERAL DEVICES AND METHODS

#4 | 2023-03-23
US20230090265A1
Electricity

Package formation methods including coupling a molded routing layer to an integrated routing layer

#5 | 2022-10-20
US20220336306A1
Electricity

Fan out package with integrated peripheral devices and methods

#6 | 2022-02-17
US20220051990A1
Electricity

FACE-UP FAN-OUT ELECTRONIC PACKAGE WITH PASSIVE COMPONENTS USING A SUPPORT

#7 | 2020-09-24
US20200303274A1
Electricity

Fan out package with integrated peripheral devices and methods

#8 | 2020-08-06
US20200251396A1
Electricity

Fan out package and methods

#9 | 2020-07-16
US20200227388A1
Electricity

Semiconductor packages, and methods for forming semiconductor packages

#10 | 2020-04-02
US20200105678A1
Electricity

Face-up fan-out electronic package with passive components using a support

#11 | 2019-12-26
US20190393154A1
Electricity

Molded substrate package in fan-out wafer level package

#12 | 2019-10-03
US20190304922A1
Electricity

Component magnetic shielding for microelectronic devices

#13 | 2019-10-03
US20190304863A1
Electricity

Fan out package with integrated peripheral devices and methods

#14 | 2019-07-11
US20190214327A1
Electricity

THERMAL CONDUCTION DEVICES AND METHODS FOR EMBEDDED ELECTRONIC DEVICES

#15 | 2019-07-04
US20190206800A1
Electricity

Molded substrate package in fan-out wafer level package

#16 | 2019-07-04
US20190206799A1
Electricity

Face-up fan-out electronic package with passive components using a support

#17 | 2019-06-27
US20190198478A1
Electricity

Package including an integrated routing layer and a molded routing layer

#18 | 2012-03-01
US20120049375A1
Electricity

Method and system for routing electrical connections of semiconductor chips

InventorID:

2551841 ⎘