Ottawa
Canada
36
2026-02-19
The entities that hold a legal rights for patent applications filed by inventor GILLINGHAM Peter B.:
Peter B. GILLINGHAM from Ottawa, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
#2 | 2024-05-23Clock mode determination in a memory system
#3 | 2023-11-30Clock mode determination in a memory system
#4 | 2023-02-16Clock mode determination in a memory system
#5 | 2021-05-06Clock mode determination in a memory system
#6 | 2020-11-12Non-volatile semiconductor memory having multiple external power supplies
#7 | 2020-04-09Clock mode determination in a memory system
#8 | 2019-06-20Non-volatile semiconductor memory having multiple external power supplies
#9 | 2019-05-30Clock mode determination in a memory system
#10 | 2018-11-01Clock mode determination in a memory system
#11 | 2017-11-09Clock mode determination in a memory system
#12 | 2017-10-26Non-volatile semiconductor memory having multiple external power supplies
#13 | 2017-06-08Clock mode determination in a memory system
#14 | 2017-04-27Non-volatile semiconductor memory having multiple external power supplies
#15 | 2016-10-06Clock mode determination in a memory system
#16 | 2016-04-07Using interrupted through-silicon-vias in integrated circuits adapted for stacking
#17 | 2016-04-07Non-volatile semiconductor memory having multiple external power supplies
#18 | 2015-09-10Clock mode determination in a memory system
#19 | 2015-06-11Semiconductor memory device with plural memory die and controller die
#20 | 2015-03-19HIGH BANDWIDTH MEMORY INTERFACE
#21 | 2015-01-15ERROR DETECTION METHOD AND A SYSTEM INCLUDING ONE OR MORE MEMORY DEVICE
#22 | 2015-01-08Clock mode determination in a memory system
#23 | 2014-10-02ASYNCHRONOUS BRIDGE CHIP
#24 | 2014-05-15Clock mode determination in a memory system
#25 | 2014-01-16Bridging device having a configurable virtual page size
#26 | 2014-01-09Simultaneous read and write data transfer
#27 | 2013-12-12HIGH BANDWIDTH MEMORY INTERFACE
#28 | 2013-11-28BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN
#29 | 2013-09-12Clock mode determination in a memory system
#30 | 2013-08-22Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
#31 | 2013-05-23High bandwidth memory interface
#32 | 2012-04-12Phase-change memory with multiple polarity bits having enhanced endurance and error tolerance
#33 | 2011-05-12Clock mode determination in a memory system
#34 | 2011-01-20Simultaneous read and write data transfer
#35 | 2010-12-30Bridging device having a frequency configurable clock domain
#36 | 2010-05-06Bridging device having a configurable virtual page size
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