Inventor profile of:

Anthony Asaro

City:

Toronto

Country:

Canada

Published Applications:

37

Last publication date:

2026-04-02

Top Assignees for applications by Anthony Asaro

The entities that hold a legal rights for patent applications filed by inventor Asaro Anthony:

Recent patent applications by Asaro Anthony

Anthony Asaro from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-04-02
US20260093623A1
Physics

MULTI-HOST REMOTE MEMORY ACCESS

#2 | 2026-01-01
US20260003655A1
Physics

GPU DIE ID VIRTUALIZATION IN CHIPLET

#3 | 2025-01-02
US20250004949A1
Physics

Extended Attributes for Shared Page Tables

#4 | 2024-06-20
US20240202015A1
Physics

Accessing Multiple Physical Partitions of a Hardware Device

#5 | 2020-08-06
US20200250787A1
Physics

Multiple application cooperative frame-based GPU scheduling

#6 | 2020-02-06
US20200042348A1
Physics

VMID as a GPU task container for virtualization

#7 | 2018-10-25
US20180307622A1
Physics

Fully virtualized TLBs

#8 | 2018-10-25
US20180307414A1
Physics

Silent active page migration faults

#9 | 2018-10-18
US20180300253A1
Physics

TRANSLATE FURTHER MECHANISM

#10 | 2018-06-21
US20180173649A1
Physics

Efficient arbitration for memory accesses

#11 | 2017-08-03
US20170220485A1
Physics

Routing direct memory access requests in a virtualized computing environment

#12 | 2017-07-27
US20170212760A1
Physics

Instruction set and micro-architecture supporting asynchronous memory access

#13 | 2017-03-23
US20170083455A1
Physics

Cache access statistics accumulation for cache line replacement selection

#14 | 2017-03-23
US20170083240A1
Physics

Selective data copying between memory modules

#15 | 2016-12-29
US20160378682A1
Physics

Access log and address translation log for a processor

#16 | 2016-12-29
US20160378674A1
Physics

Shared virtual address space for heterogeneous processors

#17 | 2016-03-03
US20160062911A1
Physics

ROUTING DIRECT MEMORY ACCESS REQUESTS IN A VIRTUALIZED COMPUTING ENVIRONMENT

#18 | 2015-04-30
US20150120978A1
Physics

Input/output memory map unit and northbridge

#19 | 2014-12-25
US20140380028A1
Physics

Virtualized device reset

#20 | 2014-02-06
US20140040565A1
Physics

Shared memory space in a unified memory model

#21 | 2014-02-06
US20140040560A1
Physics

All invalidate approach for memory management units

#22 | 2013-10-03
US20130263141A1
Physics

Visibility ordering in a memory model for a unified computing system

#23 | 2013-10-03
US20130262814A1
Physics

Mapping Memory Instructions into a Shared Memory Address Place

#24 | 2013-10-03
US20130262784A1
Physics

Memory heaps in a memory model for a unified computing system

#25 | 2013-10-03
US20130262776A1
Physics

Managing coherent memory between an accelerated processing device and a central processing unit

#26 | 2013-10-03
US20130262775A1
Physics

Cache management for memory operations

#27 | 2013-07-04
US20130174144A1
Physics

HARDWARE BASED VIRTUALIZATION SYSTEM

#28 | 2013-06-06
US20130145055A1
Physics

Peripheral Memory Management

#29 | 2013-05-30
US20130138840A1
Physics

Efficient memory and resource management

#30 | 2011-10-27
US20110264934A1
Physics

Method and apparatus for memory power management

#31 | 2011-09-08
US20110219190A1
Physics

Cache with reload capability after power restoration

#32 | 2011-03-10
US20110057939A1
Physics

Reading a local memory of a processing unit

#33 | 2010-06-24
US20100162256A1
Physics

OPTIMIZATION OF APPLICATION POWER CONSUMPTION AND PERFORMANCE IN AN INTEGRATED SYSTEM ON A CHIP

#34 | 2008-10-09
US20080250212A1
Physics

METHOD AND APPARATUS FOR ACCESSING MEMORY USING PROGRAMMABLE MEMORY ACCESSING INTERLEAVING RATIO INFORMATION

#35 | 2007-10-18
US20070245046A1
Physics

Graphics-processing system and method of broadcasting write requests to multiple graphics devices

#36 | 2007-03-08
US20070055808A1
Physics

Methods and apparatus for translating write request messages in a computing system

#37 | 2007-03-08
US20070055807A1
Physics

Methods and apparatus for translating messages in a computing system

InventorID:

278387 ⎘