Bruce B. Doris

Dielectric isolated fin with improved fin profile

Semiconductor structure having insulator pillars and semiconductor material on substrate

Dielectric isolated fin with improved fin profile

Semiconductor structure having insulator pillars and semiconductor material on substrate

STRUCTURE AND METHOD FOR SiGe FIN FORMATION IN A SEMICONDUCTOR DEVICE

Dielectric isolated fin with improved fin profile

Dielectric isolated fin with improved fin profile

Dummy gate structure for electrical isolation of a fin DRAM

Dual channel hybrid semiconductor-on-insulator semiconductor devices

Thin channel-on-insulator MOSFET device with n+ epitaxy substrate and embedded stressor

Abrupt source/drain junction formation using a diffusion facilitation layer

Thin channel-on-insulator MOSFET device with n+ epitaxy substrate and embedded stressor

Abrupt source/drain junction formation using a diffusion facilitation layer

Shallow trench isolation structures

Dielectric isolated fin with improved fin profile

Dummy gate structure for electrical isolation of a fin DRAM

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

Dense finFET SRAM

Integration of dense and variable pitch fin structures

Structure and method for forming CMOS with NFET and PFET having different channel materials

U-shaped semiconductor structure

Stacked nanowire

Trench sidewall protection for selective epitaxial semiconductor material formation

Integrated circuit including DRAM and SRAM/logic

Trench sidewall protection for selective epitaxial semiconductor material formation

Stacked nanowire

Double patterning method

Integration of dense and variable pitch fin structures

Integration of dense and variable pitch fin structures

INVERSE SIDE-WALL IMAGE TRANSFER

INVERSE SIDE-WALL IMAGE TRANSFER

Dual channel hybrid semiconductor-on-insulator semiconductor devices

Multi-height FinFETs with coplanar topography

Multi-height FinFETs with coplanar topography background

Fin structure with varying isolation thickness

Formation of semiconductor structures with variable gate lengths

Defective P-N junction for backgated fully depleted silicon on insulator MOSFET

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

Self aligned capacitor fabrication

Formation of bulk SiGe fin with dielectric isolation by anodization

Formation of bulk SiGe fin with dielectric isolation by anodization

U-shaped semiconductor structure

U-shaped semiconductor structure

Doping of FinFET structures

Three dimensional FET devices having different device widths

Extremely Thin Semiconductor-On-Insulator Field-Effect Transistor With An Epitaxial Source And Drain Having A Low External Resistance

EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR FIELD-EFFECT TRANSISTOR WITH AN EPITAXIAL SOURCE AND DRAIN HAVING A LOW EXTERNAL RESISTANCE

Self-aligned biosensors with enhanced sensitivity

Compressive strained III-V complementary metal oxide semiconductor (CMOS) device

Compressive strained III-V complementary metal oxide semiconductor (CMOS) device

Self aligned capacitor fabrication

Bulk finFET with super steep retrograde well

Bulk finFET with super steep retrograde well

Epitaxial grown extremely shallow extension region

Shallow trench isolation structures

Inducing channel stress in semiconductor-on-insulator devices by base substrate oxidation

STRAIN RELAXATION WITH SELF-ALIGNED NOTCH

STRAIN RELAXATION WITH SELF-ALIGNED NOTCH

Dense finFET SRAM

Dense finFET SRAM

Field effect transistor devices with dopant free channels and back gates

FinFET spacer formation by oriented implantation

Field effect transistor devices with dopant free channels and back gates

COMPRESSIVELY STRAINED SOI SUBSTRATE

COMPRESSIVELY STRAINED SOI SUBSTRATE

Self-aligned biosensors with enhanced sensitivity

Fin structure formation including partial spacer removal

Replacement gate ETSOI with sharp junction

Inversion mode varactor

FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL

Strained SiGe nanowire having (111)-oriented sidewalls

MOSFET gate and source/drain contact metallization

Double patterning method

Method of multiple patterning to form semiconductor devices

Semiconductor structure having NFET extension last implants

Field effect transistors with varying threshold voltages

Undercut insulating regions for silicon-on-insulator device

Semiconductor device with epitaxial source/drain facetting provided at the gate edge

Shallow trench isolation structures

Shallow trench isolation structures

Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs)

Dual shallow trench isolation liner for preventing electrical shorts

ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES

Strained thin body CMOS device having vertically raised source/drain stressors with single spacer

Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)

Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)

SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE

Inversion mode varactor

MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation and method of fabrication

Inverted thin channel mosfet with self-aligned expanded source/drain

FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE

Inverted thin channel mosfet with self-aligned expanded source/drain

Semiconductor substrate with transistors having different threshold voltages

SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES

SOI device with DTI and STI

Inversion mode varactor

Semiconductor structure having NFET extension last implants

Same-Chip Multicharacteristic Semiconductor Structures

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

Semiconductor device with a low-k spacer and method of forming the same