Stephan Rosner

METHODS, DEVICES AND SYSTEMS FOR SERIAL BUS OPERATIONS

METHODS, DEVICES AND SYSTEMS FOR HIGH SPEED TRANSACTIONS WITH NONVOLATILE MEMORY ON A DOUBLE DATA RATE MEMORY BUS

Methods, devices and systems for including alternate memory access operations over memory interface

Memory devices with low pin count interfaces, and corresponding methods and systems

Secured communication from within non-volatile memory device

Methods, devices and systems for high speed transactions with nonvolatile memory on a double data rate memory bus

Microcontroller energy profiler

Multi-ported nonvolatile memory device with bank allocation and related systems and methods

Methods, devices and systems for high speed serial bus transactions

Nonvolatile memory device with regions having separately programmable secure access features and related methods and systems

Memory device resilient to cyber-attacks and malfunction

Multi-ported nonvolatile memory device with bank allocation and related systems and methods

Memory devices, systems, and methods for updating firmware with single memory device

Nonvolatile memory device with regions having separately programmable secure access features and related methods and systems

Memory device resilient to cyber-attacks and malfunction

Memory devices, systems, and methods for updating firmware with single memory device

Encrypted gang programming

Securing data logs in memory devices

Secured communication from within non-volatile memory device

Memory devices, systems, and methods for updating firmware with single memory device

Booting an application from multiple memories

Microcontroller energy profiler

MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS

Power-Efficient Voice Activation

Booting an application from multiple memories

Managed-NAND with embedded random-access non-volatile memory

Differential File System for Computer Memory

HOST/CLIENT SYSTEM HAVING A SCALABLE SERIAL BUS INTERFACE

Host/client system having a scalable serial bus interface

Memory buffering system that improves read/write performance and provides low latency for mobile systems

Power savings apparatus and method for memory device using delay locked loop

Power-efficient voice activation

Acoustic processing unit interface for determining senone scores using a greater clock frequency than that corresponding to received audio

Apparatus and method for data capture using a read preamble

Replacing reset pin in buses while guaranteeing system recovery

System and method for maintaining RAM command timing across phase-shifted time domains

Method for improving performance in a mobile device

Using LPDDR1 bus as transport layer to communicate to flash

Memory buffering system that improves read/write performance and provides low latency for mobile systems

Byte mask command for memories

Fully associative banking for memory

Wireless computer system with latency masking

Multi media card with high storage capacity

Digital data transfer between different clock domains

Wireless computer system with queue and scheduler

Wireless computer system with queue and scheduler

System and method for improved memory performance in a mobile device

Frame based MAC control in WLAN communication devices