Inventor profile of:

Mark D. Hummel

City:

Franklin, Massachusetts

Country:

United States

Published Applications:

41

Last publication date:

2022-12-29

Top Assignees for applications by Mark D. Hummel

The entities that hold a legal rights for patent applications filed by inventor Hummel Mark D.:

Recent patent applications by Hummel Mark D.

Mark D. Hummel from Franklin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2022-12-29
US20220417176A1
Electricity

CROSSBAR MULTIPATHING FOR MULTICAST PERFORMANCE IN TILED SWITCHES

#2 | 2016-01-07
US20160004445A1
Physics

Devices and methods for interconnecting server nodes

#3 | 2015-11-26
US20150339192A1
Physics

Channel rotating error correction code

#4 | 2014-03-06
US20140068373A1
Physics

Channel rotating error correction code

#5 | 2014-03-06
US20140068220A1
Physics

HARDWARE BASED MEMORY ALLOCATION SYSTEM WITH DIRECTLY CONNECTED MEMORY

#6 | 2014-03-06
US20140068139A1
Physics

DATA TRANSFER SYSTEM AND METHOD

#7 | 2014-03-06
US20140068137A1
Physics

Virtual input/output memory management unit within a guest virtual machine

#8 | 2014-02-27
US20140056141A1
Electricity

Processing system using virtual network interface controller addressing as flow control metadata

#9 | 2014-02-06
US20140040565A1
Physics

Shared memory space in a unified memory model

#10 | 2014-02-06
US20140040560A1
Physics

All invalidate approach for memory management units

#11 | 2013-10-17
US20130275638A1
Physics

Interrupt virtualization

#12 | 2013-07-04
US20130173837A1
Physics

METHODS AND APPARATUS FOR IMPLEMENTING PCI EXPRESS LIGHTWEIGHT NOTIFICATION PROTOCOLS IN A CPU/MEMORY COMPLEX

#13 | 2013-07-04
US20130173834A1
Physics

METHODS AND APPARATUS FOR INJECTING PCI EXPRESS TRAFFIC INTO HOST CACHE MEMORY USING A BIT MASK IN THE TRANSACTION LAYER STEERING TAG

#14 | 2013-06-20
US20130159576A1
Physics

Method and apparatus for controlling system interrupts

#15 | 2013-04-04
US20130086566A1
Physics

Vector width-aware synchronization-elision for vector processors

#16 | 2012-05-17
US20120124297A1
Physics

COHERENCE DOMAIN SUPPORT FOR MULTI-TENANT ENVIRONMENT

#17 | 2012-01-19
US20120017063A1
Physics

Mechanism to handle peripheral page faults

#18 | 2011-08-25
US20110208505A1
Physics

ASSIGNING FLOATING-POINT OPERATIONS TO A FLOATING-POINT UNIT AND AN ARITHMETIC LOGIC UNIT

#19 | 2011-08-11
US20110197004A1
Physics

Processor Configured to Virtualize Guest Local Interrupt Controller

#20 | 2011-08-11
US20110197003A1
Physics

Interrupt virtualization

#21 | 2011-01-27
US20110023027A1
Physics

I/O memory management unit including multilevel address translation for I/O and computation offload

#22 | 2011-01-27
US20110022818A1
Physics

IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect

#23 | 2010-07-29
US20100191888A1
Physics

Guest interrupt manager that records interrupts for guests and delivers interrupts to executing guests

#24 | 2010-05-13
US20100122062A1
Physics

Using an IOMMU to create memory archetypes

#25 | 2010-04-15
US20100095085A1
Physics

Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU)

#26 | 2010-01-14
US20100011147A1
Physics

Virtualizing an IOMMU

#27 | 2009-12-29
US9633087
-

Implementing locks in a distributed processing system

#28 | 2008-11-20
US20080288805A1
Physics

Synchronization device and methods thereof

#29 | 2008-09-02
US10842296
-

System including a host connected to a plurality of memory modules via a serial memory interconnect

#30 | 2008-08-28
US20080209130A1
Physics

Translation data prefetch in an IOMMU

#31 | 2008-05-15
US20080114916A1
Physics

Filtering and remapping interrupts

#32 | 2008-05-15
US20080114906A1
Physics

Efficiently controlling special memory mapped system accesses

#33 | 2007-07-19
US20070168644A1
Physics

Input/output memory management unit that implements memory attributes based on translation data

#34 | 2007-07-19
US20070168643A1
Physics

Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU)

#35 | 2007-07-19
US20070168641A1
Physics

Virtualizing an IOMMU

#36 | 2007-07-19
US20070168636A1
Physics

Chained hybrid input/output memory management unit

#37 | 2007-02-15
US20070038840A1
Physics

Avoiding silent data corruption and data leakage in a virtual environment with multiple guests

#38 | 2007-02-15
US20070038839A1
Physics

Controlling an I/O MMU

#39 | 2007-02-15
US20070038799A1
Physics

Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)

#40 | 2006-06-27
US9840449
-

System and method of maintaining coherency in a distributed communication system

#41 | 2005-09-27
US9640602
-

System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system

InventorID:

303971 ⎘