Austin, Texas
United States
47
2019-01-10
The entities that hold a legal rights for patent applications filed by inventor O'Connor James M.:
James M. O'Connor from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Processor with host and slave operating modes stacked with memory
#2 | 2017-06-08Page migration in a hybrid memory device
#3 | 2016-08-11Query operations for stacked-die memory device
#4 | 2016-03-24Heterogeneous graphics processing unit for scheduling thread groups for execution on variable width SIMD units
#5 | 2016-03-03Selecting a resource from a set of resources for performing an operation
#6 | 2016-02-18Data distribution among multiple managed memories
#7 | 2015-10-15MULTI-LEVEL MEMORY HIERARCHY
#8 | 2015-07-16Page migration in a 3D stacked hybrid memory
#9 | 2015-04-09DATA PROCESSOR AND METHOD OF LANE REALIGNMENT
#10 | 2015-03-05Cache utilization and eviction based on allocated priority tokens
#11 | 2015-01-22Partitionable data bus
#12 | 2015-01-15Memory hierarchy using page-based compression
#13 | 2015-01-15Memory hierarchy using row-based compression
#14 | 2015-01-15Query operations for stacked-die memory device
#15 | 2014-12-25Spare memory external to protected memory
#16 | 2014-12-18Scheduling memory accesses using an efficient row burst value
#17 | 2014-08-07Selecting a resource from a set of resources for performing an operation
#18 | 2014-06-26Computation memory operations in a logic layer of a stacked memory
#19 | 2014-06-26High level software execution mask override
#20 | 2014-06-26Die-stacked memory device providing data translation
#21 | 2014-06-26Write endurance management techniques in the logic layer of a stacked memory
#22 | 2014-06-26Processor with host and slave operating modes stacked with memory
#23 | 2014-06-26Compound Memory Operations in a Logic Layer of a Stacked Memory
#24 | 2014-06-26Processing engine for complex atomic operations
#25 | 2014-06-26Mechanisms to bound the presence of cache blocks with specific properties in caches
#26 | 2014-06-26Mechanisms to bound the presence of cache blocks with specific properties in caches
#27 | 2014-06-26Management of cache size
#28 | 2014-06-19Dirty cacheline duplication
#29 | 2014-06-19Parity data management for a memory architecture
#30 | 2014-06-12SPILL DATA MANAGEMENT
#31 | 2014-06-05Redundant Threading for Improved Reliability
#32 | 2014-06-05Tracking Non-Native Content in Caches
#33 | 2014-05-29Creating SIMD efficient code by transferring register state through common memory
#34 | 2014-05-22Methods and apparatus for data cache way prediction based on classification as stack data
#35 | 2014-05-22METHODS AND APPARATUS FOR FILTERING STACK DATA WITHIN A CACHE MEMORY HIERARCHY
#36 | 2014-05-22Methods and apparatus for soft-partitioning of a data cache for stack data
#37 | 2014-05-22Bypassing a cache when handling memory requests
#38 | 2014-05-22Using predictions for store-to-load forwarding
#39 | 2014-05-15TRACKING MEMORY BANK UTILITY AND COST FOR INTELLIGENT POWER UP DECISIONS
#40 | 2014-05-15TRACKING MEMORY BANK UTILITY AND COST FOR INTELLIGENT SHUTDOWN DECISIONS
#41 | 2014-03-27POWER MANAGEMENT SYSTEM AND METHOD FOR A PROCESSOR
#42 | 2014-03-06Method and apparatus for power reduction during lane divergence
#43 | 2014-02-06Stacked memory device with metadata management
#44 | 2014-02-06STACKED MEMORY DEVICE WITH HELPER PROCESSOR
#45 | 2013-10-03Apparatus and Method for Fast Cache Shutdown
#46 | 2013-06-20MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS
#47 | 2011-01-11Method and system for reducing memory bandwidth requirements in an anti-aliasing operation
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