Theodorus E. Standaert

Method for fabricating finFET with merged fins and vertical silicide

finFET with merged fins and vertical silicide

Method of forming replacement metal gate with borderless contact and structure thereof

Interconnect structure for integrated circuits having improved electromigration characteristics

Structure and method of forming electrically blown metal fuses for integrated circuits

Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

Method, Computer Program and System Providing for Semiconductor Processes Optimization

Methods for forming contacts for dual stress liner CMOS semiconductor devices

Interconnect structures with encasing cap and methods of making thereof

Method of forming an embedded barrier layer for protection from chemical mechanical polishing process

STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES

Dry etchback of interconnect contacts

Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices

Embedded barrier for dielectric encapsulation

Interconnect structures with encasing cap and methods of making thereof

Dry etchback of interconnect contacts

Interconnect structures with encasing cap and methods of making thereof

Forming of local and global wiring for semiconductor product

Interlevel dielectric layer and metal layer sealing

In-situ liner formation during reactive ion etch