Jun Wan

CORRECTIVE READ WITH PARALLEL AUTO-READ CALIBRATION IN A MEMORY SUB-SYSTEM

DIFFERENTIAL WORDLINE SCAN IN A MEMORY SUB-SYSTEM

MEMORY DEVICE BAD COLUMN IDENTIFICATION AND COMPENSATION

Corrective read with parallel auto-read calibration in a memory sub-system

PROGRAM AND READ OPERATIONS USING UNBALANCED READ WINDOW BUDGETS ACROSS PAGE TYPES

READ THRESHOLD MANAGEMENT USING PAGE TYPE

BIN-BASED READ ERROR HANDLING FLOWS USING A FAST CORRECTIVE READ OPERATION

FILTERING METRICS ASSOCIATED WITH MEMORY

ERASE DISTRIBUTION TIGHTENING TO IMPROVE READ BUDGET WINDOW IN A MEMORY SUB-SYSTEM

TEMPERATURE-BASED CHARGE PUMP CONTROL

PROGRAMMING DATA IN MEMORY

VALLEY CHECK MEMORY SYSTEM COMMAND

PERFORMING CORRECTIVE SENSE OPERATIONS IN MEMORY

MULTI-FINE PROGRAM SCHEME FOR RELIABILITY RISK WORD LINES

3D NAND MEMORY WITH FAST CORRECTIVE READ

ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICE

RELIABILITY IMPROVEMENTS USING MEMORY DIE BINNING

WORD LINE BASED PROGRAM VOLTAGE ADJUSTMENT

TEMPERATURE SENSOR MANAGEMENT DURING ERROR HANDLING OPERATIONS IN A MEMORY SUB-SYSTEM

PROGRAM VERIFY COMPENSATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK

READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME

Filtering metrics associated with memory

3D NAND memory with fast corrective read

Method to optimize first read versus second read margin by switching boost timing

Techniques for reading memory cells in a memory device during a multi-pass programming operation

Multi-pass programming operation sequence in a memory device

Smart early detection of wordline-memory hole defects with wordline-dependent dual sensing during erase verify

Non-volatile memory with data refresh based on data states of adjacent memory cells

Variable programming voltage step size control during programming of a memory device

Dynamic sense node voltage to compensate for variances when sensing threshold voltages of memory cells

Reduced verify scheme during programming based on spacing between verify levels

Mitigating grown bad blocks

First read countermeasures in memory

First read countermeasures in memory

Charge storage region in non-volatile memory

Charge storage region in non-volatile memory

Adaptive temperature and memory parameter throttling

Open block source bias adjustment for an incompletely programmed block of a nonvolatile storage device

System and method for refreshing data in a memory device

Memory cells using multi-pass programming

Systems and methods for lower page writes

On chip dynamic read level scan and error detection for nonvolatile storage

Word line coupling for deep program-verify, erase-verify and read

Systems and methods for lower page writes

Block and page level bad bit line and bits screening methods for program algorithm

On chip dynamic read level scan and error detection for nonvolatile storage

Aggregating data latches for program level determination

Non-volatile storage with read process that reduces disturb

Wordline-to-wordline stress configuration

Detection of broken word-lines in memory arrays

Reducing neighbor read disturb

Erase and programming techniques to reduce the widening of state distributions in non-volatile memories

Verification process for non-volatile storage

Data coding for improved ECC efficiency

Dynamically adjustable erase and program levels for non-volatile memory

Built in on-chip data scrambler for non-volatile memory

Method for scrambling data in which scrambling data and scrambled data are stored in corresponding non-volatile memory locations

Intelligent control of program pulse for non-volatile storage

Verification process for non-volatile storage

Reducing programming voltage differential nonlinearity in non-volatile storage

Method for forming dual bit line metal layers for non-volatile memory

Dual bit line metal layers for non-volatile memory

Intelligent control of program pulse duration

Non-volatile storage system with intelligent control of program pulse duration