Bin YU

Germanium MOSFET devices and methods for making same

Double and triple gate MOSFET devices and methods for making same

Double and triple gate MOSFET devices and methods for making same

Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin

Methods for forming small contacts

Germanium MOSFET devices and methods for making same

FinFET device with multiple fin structures

Growth method for chalcongenide phase-change nanostructures

Reversed T-shaped finfet

Systems and methods for forming multiple fin structures using metal-induced-crystallization

Formation of semiconductor devices to achieve <100> channel orientation

FinFET device with multiple channels

Strained-silicon device with different silicon thicknesses

Scanning laser thermal annealing

SRAM formation using shadow implantation

SRAM formation using shadow implantation

Flash memory device

Tri-gate and gate around MOSFET devices and methods for making same

Double gate semiconductor device having a metal gate

Reversed T-shaped FinFET

Method for doping structures in FinFET devices

Doped structure for finfet devices

Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal

Doped structure for FinFET devices

Flash memory device

Epitaxially grown fin for FinFET

Methods for forming small contacts

Germanium MOSFET devices and methods for making same

Smooth fin topology in a FinFET device

End-of-range defect minimization in semiconductor device

Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices

Fully silicided gate structure for FinFET devices

Sacrificial oxide for minimizing box undercut in damascene FinFET

Method of forming merged FET inverter/logic gate

Method of manufacturing metal gate MOSFET with strained channel

Narrow body raised source/drain metal gate MOSFET

Source and drain protection and stringer-free gate formation in semiconductor devices

Method for forming a tri-gate MOSFET

Semiconductor device with fully silicided source/drain and damascence metal gate

Method of forming miniaturized polycrystalline silicon gate electrodes using selective oxidation

Isolated FinFET P-channel/N-channel transistor pair

Damascene gate semiconductor processing with local thinning of channel region

Non-volatile memory device

Semiconductor device having a gate structure surrounding a fin

Non-volatile memory device

Selective silicidation of gates in semiconductor devices to achieve multiple threshold voltages

Strained-silicon devices with different silicon thicknesses

SRAM formation using shadow implantation

Narrow fin FinFET

Method for improving MOS mobility

Damascene tri-gate FinFET

Narrow-body damascene tri-gate FinFET

Merged FinFET P-channel/N-channel pair

Semiconductor device having a thin fin and raised source/drain areas

Flash memory device

Low-temperature post-dopant activation process

Multi-step chemical mechanical polishing of a gate area in a FinFET

Strained channel FinFET

Self aligned damascene gate

System and method for forming stacked fin structure using metal-induced-crystallization

Semiconductor device with silicide source/drain and high-K dielectric

Shallow trench isolation (STI) region with high-K liner and method of formation

Additional gate control for a double-gate MOSFET

Method for forming multiple fins in a semiconductor device

Dual silicon layer for chemical mechanical polishing planarization

Polysilicon tilting to prevent geometry effects during laser thermal annealing

Damascene finfet gate with selective metal interdiffusion

Method for forming tri-gate FinFET with mesa isolation

Multi-step chemical mechanical polishing of a gate area in a FinFET

Varying carrier mobility in semiconductor devices to achieve overall design goals

Method for forming structures in finfet devices

Double-gate semiconductor device

Method of manufacturing a semiconductor device having a fin structure