Inventor profile of:

Simon Li

City:

Cupertino, California

Country:

United States

Published Applications:

23

Last publication date:

2024-09-19

Top Assignees for applications by Simon Li

The entities that hold a legal rights for patent applications filed by inventor Li Simon:

Recent patent applications by Li Simon

Simon Li from Cupertino, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-09-19
US20240313135A1
Electricity

SYNCHRONOUS WIRED-OR ACK STATUS FOR MEMORY WITH VARIABLE WRITE LATENCY

#2 | 2024-08-08
US20240264972A1
Physics

Interface with Variable Data Rate

#3 | 2023-02-16
US20230051578A1
Physics

Interface with variable data rate

#4 | 2022-03-10
US20220077327A1
Electricity

Synchronous wired-or ACK status for memory with variable write latency

#5 | 2020-09-17
US20200295974A1
Electricity

Serial link receiver with improved bandwidth and accurate eye monitor

#6 | 2020-06-04
US20200176617A1
Electricity

Synchronous wired-OR ACK status for memory with variable write latency

#7 | 2020-05-21
US20200159688A1
Physics

Interface with variable data rate

#8 | 2019-06-06
US20190173661A1
Electricity

Phase calibration of clock signals

#9 | 2019-05-16
US20190149366A1
Electricity

Serial link receiver with improved bandwidth and accurate eye monitor

#10 | 2018-11-15
US20180329859A1
Physics

Interface with variable data rate

#11 | 2018-01-11
US20180013544A1
Electricity

Phase calibration of clock signals

#12 | 2017-08-31
US20170250840A1
Electricity

Serial link receiver with improved bandwidth and accurate eye monitor

#13 | 2017-06-22
US20170177540A1
Physics

Interface with variable data rate

#14 | 2017-05-25
US20170147234A1
Physics

Synchronous wired-OR ACK status for memory with variable write latency

#15 | 2017-01-05
US20170005785A1
Electricity

Phase calibration of clock signals

#16 | 2016-05-05
US20160124895A1
Physics

Interface with variable data rate

#17 | 2015-10-29
US20150310903A1
Physics

Supporting calibration for sub-rate operation in clocked memory systems

#18 | 2015-04-02
US20150092869A1
Electricity

Interface with variable data rate

#19 | 2014-02-13
US20140047158A1
Physics

Synchronous wired-or ACK status for memory with variable write latency

#20 | 2013-11-14
US20130301368A1
Physics

Supporting calibration for sub-rate operation in clocked memory systems

#21 | 2013-06-13
US20130148709A1
Electricity

Interface with variable data rate

#22 | 2013-01-10
US20130013878A1
Physics

Levelization of memory interface for communicating with multiple memory devices

#23 | 2010-04-29
US20100103994A1
Physics

Interface with variable data rate

InventorID:

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