Eric A. Joseph

Method of integrated circuit (IC) chip fabrication

Directed self-assembly for copper patterning

Thin film interconnects with large grains

Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication

Interconnect structure including airgaps and substractively etched metal lines

Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etch

Selective sputtering with light mass ions to sharpen sidewall of subtractively patterned conductive metal layer

Spin torque MRAM fabrication using negative tone lithography and ion beam etching

High aspect ratio patterning of hard mask materials by organic soft masks

Low temperature encapsulation for magnetic tunnel junction

Hybrid subtractive etch/metal fill process for fabricating interconnects

Hybrid subtractive etch/metal fill process for fabricating interconnects

Nano deposition and ablation for the repair and fabrication of integrated circuits

Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication

Spin torque MRAM fabrication using negative tone lithography and ion beam etching

Spin torque MRAM fabrication using negative tone lithography and ion beam etching

Interconnects based on subtractive etching of silver

Wet clean process for removing CHFetch residue

Hybrid subtractive etch/metal fill process for fabricating interconnects

HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS

Hybrid subtractive etch/metal fill process for fabricating interconnects

Low resistance metal contacts to interconnects

Low resistance metal contacts to interconnects

Interconnects based on subtractive etching of silver

Thin film interconnects with large grains

Etch rate enhancement for a silicon etch process through etch chamber pretreatment

Sidewall image transfer for heavy metal patterning in integrated circuits

Sputter and surface modification etch processing for metal patterning in integrated circuits

Nano deposition and ablation for the repair and fabrication of integrated circuits

Wet clean process for removing CHFetch residue

CATALYTIC ETCH WITH MAGNETIC DIRECTION CONTROL

Fabricating a small-scale radiation detector

Subtractive plasma etching of a blanket layer of metal or metal alloy

Sputter etch processing for heavy metal patterning in integrated circuits

Self-aligned pitch split for unidirectional metal wiring

Self-aligned pitch split for unidirectional metal wiring

Catalytic etch with magnetic direction control

Nanopore sensor device

Nanopore sensor device

Small footprint phase change memory cell

Patterning transition metals in integrated circuits

Patterning transition metals in integrated circuits

Uniform critical dimension size pore for PCRAM application

SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS

SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS

Sputter and surface modification etch processing for metal patterning in integrated circuits

High aspect ratio and reduced undercut trench etch process for a semiconductor substrate

Thermally insulated phase change material cells

INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN

High aspect ratio and reduced undercut trench etch process for a semiconductor substrate

Borderless self-aligned metal contact patterning using printable dielectric materials

HEAT SHIELD LINER IN A PHASE CHANGE MEMORY CELL

Silicide micromechanical device and methods to fabricate same

Magnetic spin shift register memory

Pore phase change material cell fabricated from recessed pillar

Methods to fabricate silicide micromechanical device

Pillar-based interconnects for magnetoresistive random access memory

Flat lower bottom electrode for phase change memory cell

Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process

Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process

Thermally insulated phase material cells

Thermally insulated phase change material memory cells

Method to reduce a via area in a phase change memory cell

In via formed phase change memory cell with recessed pillar heater

Field effect transistor having nanostructure channel

Interconnect structure for improved time dependent dielectric breakdown

Small footprint phase change memory cell

Magnetic spin shift register memory

Phase change memory device with plated phase change material

Pore phase change material cell fabricated from recessed pillar

In via formed phase change memory cell with recessed pillar heater

Pillar-based interconnects for magnetoresistive random access memory

Flat lower bottom electrode for phase change memory cell

Phase change memory device with plated phase change material

Thermally insulated phase change material memory cells with pillar structure

METHOD TO REDUCE RESET CURRENT OF PCM USING STRESS LINER LAYERS

Method to reduce a via area in a phase change memory cell

Nanoscale electrodes for phase change memory devices

Phase change memory with tapered heater

Phase change material with filament electrode

Method of forming ring electrode

Pore phase change material cell fabricated from recessed pillar

METHOD TO ENHANCE PERFORMANCE OF COMPLEX METAL OXIDE PROGRAMMABLE MEMORY

Phase change material with filament electrode

Self aligned ring electrodes

Method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices

Phase change memory cell with electrode

Phase change memory with tapered heater

Programmable-resistance memory cell