Alexander E. Andreev

Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same

System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units

System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units

System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors

Serializer-deserializer (SerDes) having a predominantly digital architecture and method of deserializing data

Built in test controller with a downloadable testing program

Command language for memory testing

Method and system for outputting a sequence of commands and data described by a flowchart

Memory mapping for parallel turbo decoding

System and method for efficiently testing a large random access memory space

Sequential tester for longest prefix search engines

Digital Gaussian noise simulator

Digital gaussian noise simulator

Method and system for outputting a sequence of commands and data described by a flowchart

Search engine for large-width data

Method and system for mapping netlist of integrated circuit to design

Method and system for converting netlist of integrated circuit between libraries

RRAM memory error emulation

Sequential tester for longest prefix search engines

Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2

Decomposer for parallel turbo decoding, process and integrated circuit

Optimizing depths of circuits for Boolean functions

Decomposer for parallel turbo decoding, process and integrated circuit

Built-in functional tester for search engines

Memory BISR controller architecture

Memory BISR architecture for a slice

Method and BIST architecture for fast memory testing in platform-based integrated circuit

Integrated circuit and process for identifying minimum or maximum input value among plural inputs

RRAM communication system

Method for generating tech-library for logic function

Verification of RRAM tiling netlist

Pseudo-random one-to-one circuit synthesis

Decision function generator for a Viterbi decoder

FFS search and edit pipeline separation

Compact custom layout for RRAM column controller

Table module compiler equivalent to ROM

Method and system for outputting a sequence of commands and data described by a flowchart

Yield driven memory placement system

Process and apparatus for placing cells in an IC floorplan

Process and apparatus for memory mapping

Clock tree synthesis with skew for memory devices

User selectable editing protocol for fast flexible search engine

Built-in test for multiple memory circuits

Optimization of adder based circuit architecture

Method for evaluating logic functions by logic circuits having optimized number of and/or switches

Method for evaluating logic functions by logic circuits having optimized number of and/or switches

Process and apparatus for placement of cells in an IC during floorplan creation

FIFO memory with single port memory modules for allowing simultaneous read and write operations

Memory that allows simultaneous read requests

Process and apparatus for fast assignment of objects to a rectangle

Method for optimizing execution time of parallel processor programs

Controller architecture for memory mapping

Data stream frequency reduction and/or phase shift

Memory mapping for parallel turbo decoding

Universal gates for ICs and transformation of netlists for their implementation

Netlist redundancy detection and global simplification

Method and apparatus of IC implementation based on C++ language description

Symbolic simulation driven netlist simplification