Inventor profile of:

Stefan Slesazeck

City:

Dresden

Country:

Germany

Published Applications:

14

Last publication date:

2010-05-06

Top Assignees for applications by Stefan Slesazeck

The entities that hold a legal rights for patent applications filed by inventor Slesazeck Stefan:

Recent patent applications by Slesazeck Stefan

Stefan Slesazeck from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2010-05-06
US20100110753A1
Electricity

Ferroelectric Memory Cell Arrays and Method of Operating the Same

#2 | 2010-01-21
US20100014372A1
Physics

Semiconductor Device, an Electronic Device and a Method for Operating the Same

#3 | 2009-12-03
US20090296449A1
Physics

Integrated circuit and method of operating an integrated circuit

#4 | 2009-08-27
US20090213648A1
Physics

Integrated circuit comprising a thyristor and method of controlling a memory cell comprising a thyristor

#5 | 2009-07-16
US20090179262A1
Electricity

Floating Body Memory Cell with a Non-Overlapping Gate Electrode

#6 | 2009-05-21
US20090129145A1
Physics

Memory cell array comprising floating body memory cells

#7 | 2009-03-05
US20090057778A1
Electricity

Integrated circuit and method of manufacturing an integrated circuit

#8 | 2008-12-18
US20080308870A1
Electricity

INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE

#9 | 2008-12-04
US20080299722A1
Electricity

Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure

#10 | 2008-10-16
US20080253179A1
Physics

Semiconductor device, an electronic device and a method for operating the same

#11 | 2007-02-15
US20070034927A1
Electricity

Trench storage capacitor

#12 | 2006-11-02
US20060244024A1
Electricity

Memory cell array and method of manufacturing the same

#13 | 2006-10-19
US20060234451A1
Electricity

Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor

#14 | 2005-02-17
US20050036392A1
Electricity

Architecture and fabrication method of a vertical memory cell

InventorID:

3608878 ⎘