Inventor profile of:

Stephan Wege

City:

Dresden

Country:

Germany

Published Applications:

19

Last publication date:

2010-12-30

Top Assignees for applications by Stephan Wege

The entities that hold a legal rights for patent applications filed by inventor Wege Stephan:

Recent patent applications by Wege Stephan

Stephan Wege from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2010-12-30
US20100330805A1
Electricity

METHODS FOR FORMING HIGH ASPECT RATIO FEATURES ON A SUBSTRATE

#2 | 2009-12-31
US20090321940A1
Electricity

Method for Manufacturing Contact Openings, Method for Manufacturing an Integrated Circuit, an Integrated Circuit

#3 | 2009-09-24
US20090239314A1
Electricity

Methods of Manufacturing a Semiconductor Device

#4 | 2009-09-03
US20090219496A1
Physics

Methods of Double Patterning, Photo Sensitive Layer Stack for Double Patterning and System for Double Patterning

#5 | 2009-07-02
US20090166318A1
Electricity

Method of Fabricating an Integrated Circuit

#6 | 2009-05-21
US20090127722A1
Electricity

Method for Processing a Spacer Structure, Method of Manufacturing an Integrated Circuit, Semiconductor Device and Intermediate Structure with at Least One Spacer Structure

#7 | 2009-05-07
US20090115027A1
Electricity

Method of Fabricating an Integrated Circuit

#8 | 2009-04-23
US20090102023A1
Electricity

Method for Manufacturing a Structure, Semiconductor Device and Structure on a Substrate

#9 | 2009-03-26
US20090081876A1
Electricity

Method of preventing etch profile bending and bowing in high aspect ratio openings by treating a polymer formed on the opening sidewalls

#10 | 2009-02-05
US20090033362A1
Electricity

Method for forming a structure on a substrate and device

#11 | 2008-04-17
US20080090101A1
Electricity

Method of preparing a coating solution and a corresponding use of the coating solution for coating a substrate

#12 | 2007-10-04
US20070232070A1
Electricity

Method and device for depositing a protective layer during an etching procedure

#13 | 2007-05-31
US20070123045A1
Electricity

Method for the treatment of material, in particular in the fabrication of semiconductor components

#14 | 2007-05-17
US20070111339A1
Electricity

Apparatus for processing a substrate

#15 | 2005-10-27
US20050239223A1
Physics

Method and device for monitoring the etching operation for a regular depth structure in a semiconductor substrate

#16 | 2005-09-08
US20050196952A1
Electricity

Method for production of a semiconductor structure

#17 | 2005-07-07
US20050148193A1
Electricity

Photolithographic method for forming a structure in a semiconductor substrate

#18 | 2005-05-26
US20050112506A1
Electricity

Photolithographic patterning process using a carbon hard mask layer of diamond-like hardness produced by a plasma-enhanced deposition process

#19 | 2005-05-24
US10219885
-

Method for etching high-aspect-ratio features

InventorID:

3724079 ⎘