Poughkeepsie, New York
United States
15
2009-12-17
The entities that hold a legal rights for patent applications filed by inventor Tessier Brian L.:
Brian L. Tessier from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
METHOD OF FABRICATING A GATE STRUCTURE
#2 | 2009-06-25Field effect device with reduced thickness gate
#3 | 2009-04-23METHOD OF FABRICATING A GATE STRUCTURE AND THE STRUCTURE THEREOF
#4 | 2009-01-01Method of forming a guard ring or contact to an SOI substrate
#5 | 2008-11-20METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE
#6 | 2008-07-24STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE
#7 | 2008-05-15Poly filled substrate contact on SOI structure
#8 | 2007-12-06METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE AND RELATED STRUCTURES
#9 | 2007-09-27Field effect device with reduced thickness gate
#10 | 2007-08-23Poly filled substrate contact on SOI structure
#11 | 2007-07-12Semiconductor device structure having low and high performance devices of same conductive type on same substrate
#12 | 2007-01-25Undercut and residual spacer prevention for dual stressed layers
#13 | 2007-01-11Self-aligned dual stressed layers for NFET and PFET
#14 | 2005-12-15A MANUFACTURABLE METHOD AND STRUCTURE FOR DOUBLE SPACER CMOS WITH OPTIMIZED NFET/PFET PERFORMANCE
#15 | 2005-02-22MOSFET device with in-situ doped, raised source and drain structures
3842998 ⎘