Inventor profile of:

Andrew Herbert Simon

City:

Fishkill, New York

Country:

United States

Published Applications:

15

Last publication date:

2026-02-12

Top Assignees for applications by Andrew Herbert Simon

The entities that hold a legal rights for patent applications filed by inventor Simon Andrew Herbert:

Recent patent applications by Simon Andrew Herbert

Andrew Herbert Simon from Fishkill, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-02-12
US20260047411A1
Electricity

DAMASCENE INTERCONNECTS WITH BILAYER LINER

#2 | 2025-10-02
US20250309099A1
Electricity

DIRECTIONAL CONDUCTOR INTERCONNECT WITH EMBEDDED VIA

#3 | 2024-07-04
US20240222448A1
Electricity

MIDDLE OF THE LINE ARCHITECTURE WITH SUBTRACTIVE SOURCE/DRAIN CONTACT

#4 | 2024-06-27
US20240215462A1
Electricity

MEMORY CELL WITH A VARIABLE ELEMENT AND A PHASE CHANGE MEMORY

#5 | 2023-03-30
US20230098562A1
Electricity

PHASE CHANGE MEMORY CELL SIDEWALL PROJECTION LINER

#6 | 2023-03-30
US20230094466A1
Electricity

NANOSHEET TRANSISTORS WITH BURIED POWER RAILS

#7 | 2023-03-16
US20230085288A1
Electricity

ELECTRICALLY INSULATED PROJECTION LINER FOR AI DEVICE

#8 | 2023-03-09
US20230075622A1
Electricity

Confined bridge cell phase change memory

#9 | 2023-02-23
US20230058218A1
Electricity

Phase change memory cell spacer

#10 | 2022-06-09
US20220181547A1
Electricity

Phase change memory cell with a projection liner

#11 | 2022-06-09
US20220181546A1
Electricity

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

#12 | 2009-06-18
US20090151981A1
Electricity

Gap free anchored conductor and dielectric structure and method for fabrication thereof

#13 | 2008-11-04
US11958691
-

Gap free anchored conductor and dielectric structure and method for fabrication thereof

#14 | 2007-07-10
US10318606
-

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

#15 | 2005-09-27
US10318605
-

Method for depositing a metal layer on a semiconductor interconnect structure

InventorID:

3966931 ⎘