Inventor profile of:

Lei Fu

City:

Austin, Texas

Country:

United States

Published Applications:

26

Last publication date:

2025-01-16

Top Assignees for applications by Lei Fu

The entities that hold a legal rights for patent applications filed by inventor Fu Lei:

Recent patent applications by Fu Lei

Lei Fu from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-01-16
US20250022847A1
Electricity

HYBRID BONDED INTERCONNECT BRIDGING

#2 | 2023-11-30
US20230387076A1
Electricity

Hybrid bonded interconnect bridging

#3 | 2023-09-28
US20230307405A1
Electricity

ELECTRONIC DEVICE INCLUDING DIES AND AN INTERCONNECT COUPLED TO THE DIES AND PROCESSES OF FORMING THE SAME

#4 | 2022-10-06
US20220319871A1
Electricity

Molded chip package with anchor structures

#5 | 2022-02-17
US20220052023A1
Electricity

Hybrid bonded interconnect bridging

#6 | 2021-06-24
US20210193604A1
Electricity

Semiconductor chip with reduced pitch conductive pillars

#7 | 2021-03-04
US20210066144A1
Electricity

Semiconductor chip with solder cap probe test pads

#8 | 2021-02-25
US20210057352A1
Electricity

Fan-out package with reinforcing rivets

#9 | 2021-01-21
US20210020459A1
Electricity

Molded chip package with anchor structures

#10 | 2020-11-19
US20200365543A1
Electricity

Semiconductor chip with reduced pitch conductive pillars

#11 | 2020-09-17
US20200294923A1
Electricity

Multi-RDL structure packages and methods of fabricating the same

#12 | 2020-01-30
US20200035606A1
Electricity

Multi-RDL structure packages and methods of fabricating the same

#13 | 2019-10-24
US20190326257A1
Electricity

HIGH DENSITY FAN-OUT PACKAGING

#14 | 2019-02-14
US20190051633A1
Electricity

Molded chip combination

#15 | 2015-10-01
US20150279773A1
Electricity

Stacked semiconductor chips packaging

#16 | 2013-12-26
US20130341802A1
Electricity

Integrated circuit package having offset vias

#17 | 2013-12-26
US20130341785A1
Electricity

SEMICONDUCTOR CHIP WITH EXPANSIVE UNDERBUMP METALLIZATION STRUCTURES

#18 | 2013-08-29
US20130221517A1
Electricity

Semiconductor workpiece with backside metallization and methods of dicing the same

#19 | 2012-08-02
US20120193788A1
Electricity

STACKED SEMICONDUCTOR CHIPS PACKAGING

#20 | 2012-03-15
US20120061853A1
Electricity

Semiconductor chip device with underfill

#21 | 2012-03-01
US20120049343A1
Electricity

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

#22 | 2011-02-10
US20110031603A1
Electricity

Semiconductor devices having stress relief layers and methods for fabricating the same

#23 | 2010-08-19
US20100207250A1
Electricity

Semiconductor chip with protective scribe structure

#24 | 2009-12-10
US20090302427A1
Electricity

Semiconductor chip with reinforcement structure

#25 | 2009-03-12
US20090065952A1
Electricity

Semiconductor chip with crack stop

#26 | 2008-08-14
US20080191318A1
Electricity

SEMICONDUCTOR DEVICE AND METHOD OF SAWING SEMICONDUCTOR DEVICE

InventorID:

409847 ⎘