Edoardo Prete

Data sampler including a first stage and a second stage

Method and apparatus for phase detection

Memory system with a retiming circuit and a method of exchanging data and timing signals between a memory controller and a memory device

Clock and data recovery circuit having gain control

Clock and data recovery circuit including first and second stages

Receiving data over channels with intersymbol interference

Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signals

Clock signal extraction device and method for extracting a clock signal from data signal